• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.220-227
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• 2002

An one-dimensional VLSI array for high speed processing of Fractal image compression was designed. Using again the overlapped input data of adjacent domain blocks in the existing one-dimensional VLSI array, we can save the number of total input for the operations, and so we can save the total computation time. In the design procedure, we considered the data dependences between the input data, reordered the input data to the array, and designed the processing elements. Registers and multiplexors are added for the storing and routing of the input data in some processing elements. Consequently as adding a little hardware, this design shows (N-4B)/4(N-B) times of speed-up compared with the existing array, where N is image size and B is block size.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.81-86
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• 2003

Current growth of VLSI design depends critically on the research and development of automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms performing placement and routing impact on performance and area of VLSI design. Switchbox routing is a problem interconnecting each terminals on all four sides of the region, unlike channel routing. In this paper we propose a genetic algorithm searching solution space for switchbox routing problem. We compare the performance of proposed genetic algorithm(GA) for switchbox routing with that of other switchbox routing algorithm by analyzing the results of each implementation. Consequently experimental results show that out proposed algorithm reduce routing length and number of the via over the other switchbox routing algorithms.

• Information and Communications Magazine
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• v.9 no.9
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• pp.72-85
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• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.433-442
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• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.1
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• pp.83-90
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• 1994

In this paper, the GYRATOR circuit is designed by the highly linear MOS transconductor with the gain factor controllable by offset voltage, and the floating inductor, the floating resistor and the grounded resistor are simulated by the GYTATOR for VLSI. And for the design exmple, Butterworth filter is designed using this GYRATOR, and is conpensated by the frequency transformation for the frequency shift that due to non-ideal output impedance of transconductor.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.63-69
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• 1998

The area optimization of the power distribution network is an important problem in the layout design of VLSI systems. In this paper we propose noval methods to solve the problem of designing minimal area power distribution nets, while satisfying voltage drop and electromigration constraints. We propose two novel greedy heuristics for power net design-one based on bottom-up tree construction using greedy merging and the other based on top-down linearly separable partitioning.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1081-1091
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• 1992

A new method for designing of WDF(Wave Digital Filter) is proposed, which is based on the digital dependent port adaptor transformed by the VGIC(Voltage Conversion Generalized Impedance Converter). To design the WD-LPF, WD-BPF, WD-HPF, or WD-BRF with CGIC(Current Conversion GIC). we have to use the different structure respectively. But the proposed method to design any types of WDF requires only one universal WDF structure, and this structure is attractive for its VLSI implementation for its simplicity.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.4
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• pp.20-26
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• 2000

In the recently our 21C, it is a necessary to provide the VLSI design education methods based on the electronic information systems. In this paper, we will show a education model of the venture study programs concern with Micro-Robot making. The development education systems apply into the industrial fields from the specification major module instruction including improve the VLSI design capability using the Micro-Robot making for information communication techniques. Also, the development instruction model provides one in the field system to the industrial applications specification technical staffs and VLSI design for the venture education programs. We expect the proposed education systems extended into a new venture instruction program sets for technical major members.