• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.91_92
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• 2009

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.845-849
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• 1987

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and basis conversion algorithms. In this paper, a new multiplication circuit is developed for the finite field GF($2^m$) based on a conventional basis. It is composed of AND gates and EXCLUSIVE-OR gates and is regular, simple, expandable and therefore, naturally suitable for VLSI implementations.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.1-4
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• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1839-1849
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• 1989

An optimal variable assignment algorithm is presented as a decomposition method of MVL functions. A given 3-valued combinational logic function is disintegrated into subfunction composed of the function dependant relation, then extracted implicant output elements from subfunctions are assigned to a T-gates. As a circuit implementation tool, a programmable integarated T-gate module is proposed, and the construction procedure of combinational MVL functions is systematized in each step. This method is expected to give properties of the systematic procedure, possibility of T-gate number reduction, unification of module, and flexibility of module composition. Specially variable decomposition method can be pointed out as an approach to solving the limitation problem of the input and output terminal number in VLSI implementations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2966-2977
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• 1996

As design of very large circuits is made possible by rapid development of VLSI technologies, efficient fault simulation is needed. Ingeneral, fault simulation requires many computer resources. As general-purpose multiprocessors become more common and affordable, these seem to be an attractive and effective alternative for fault simulation. Efficient fault simulation of synchronous sequential circuits has been reported to be attainably by using a linear iterative array model for such a circuit, and combining parallel fault simulation with russogate fault simulation. Such fault simulation algorithm is parallelized on a general-purpose multiprocessor with shard memory for acceleration of fault simulation. Through the experimenal study, the effect of the number of processors on speed-up of simulation, processor utilization, and the effect of multiprocessor hardware on simulation performance are studied. Some results for experiments with benchmark circuits are shown.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.1
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• pp.54-59
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• 2002

In the three-axis control of satellites by using on-board actuators, gyros are usually used to measure the attitude angles and angular rates. The gyros are operated by electronic parts and mechanical actuators. The digital components of the electronic parts consist of largely FPGA (Field Programmable Gate Array) as one of the methods for VLSI(Very Large Scale Integrated) circuit design, while the mechanical parts provide output signal directly by mechanical actuation of a spinning rotor. In this research, a mixed mode of gyro is implemented in FGA. In addition to the hardware implementation, the simulation study was conducted by using the SABER for the mixed mode simulator. Results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are also presented to validate the FPGA implementation.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.40-45
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• 1994

The TCAD(Technology Computer Aided Design) software tool is a popular name to be able to simulate the semiconductor process and device circuit. We have developed a two-dimensional TCAD software tool included an editor, parser, each process unit, and 2D, 3D graphic routine that is Integrated Environment. The initial grid for numerical analysis is automatically generated with the geometric series that use the user default(given) line and position separated with grid interval and the nodes corresponding to each mesh point stoic the all the possible attribute. Also, we made a data structure called PIF for input or output. Methods of ion implantation in this paper arc Monte Carlo, Gaussian Pearson and Dual-Pearson. Analytical model such as Gaussian, Pearson and Dual-Pearson were considered the multilayer structure and two-dimensional tilted implantation. We simuttaneously calculated the continuity equation of impurity and point defect in diffusion simulation. Oxidation process was simulated by analytical ERFC(Complementary Error Function) model for local oxidation.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.30-30
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• 2000

In the three axis control of satellite by using reaction wheel and gyro, a Gyro carries out measuring of the attitude angie and the attitude angular velocity. The Gyro is operated by the electronic part and the mechanic actuator. The digital part of the electronic part is consisted of the FPGA (Field Programmable Gate Array), which is one of the methods for designing VLSI (Very Large Scale Integrated Circuit), and the mechanic actuator processes the input/output data by the dynamic model. In the research of the mixed mode of Gyro, the simulation is accomplished by SABER of the mixed mode simulator and the results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are proposed.