• 대한전자공학회논문지
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• 제25권8호
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• pp.998-1009
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• 1988

A Hierarchical Circuit Extract Algotithm, which efficiently extract circuits from VLSI mask pattern information, is programmed. Quad-tree is used as a data structure which includes various CIF circuit elements and instances. This system is composed of CIF input routine, Quad-tree making routine, Transistor finding routine and Connection list making routine. This circuit extractor can extract circuit with hierarchical structure of circuit. This system is designed using YACC and LEX. By programming this algorithm with C language and adopting to various circuits, the effectiveness of this algorithm is showed.

• 한국컴퓨터산업학회논문지
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• 제7권3호
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• pp.205-215
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• 2006

본 논문에서는 최근의 64비트 마이크로프로세서에 대해서 PLA설계법 및 검사가 쉽고 용이하도록 하는 방법에 대해서 논하였다. VLSI에서 RAM. ROM. PLA를 사용한 설계법이 정착 되어가고 있으며 PLA는 논리설계와 회로변경 및 검사가 용이하기 때문에 성능과 가격이 중요하다. 향후에도 PLA는 VLSI 설계의 기본요소로서 중요한 위치를 점유할 것이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.975-978
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• 1999

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• 융합신호처리학회논문지
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• 제8권1호
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• pp.73-77
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• 2007

본 논문에서는 적응 필터링 분야에서 널리 쓰이고 있는 재귀형 LMS 필터의 고속연산을 위해 Cyclo-static 스케줄러를 이용하여 VLSI구현에 적합한 구조를 제안한다. 이과정은 크게 스케줄 생성 단계와 회로도 생성 단계로 구성되는데, 스케줄 생성단계는 입력으로서 Fully Specified Flow Graph(FSFG)로 표현된 재귀 DSP 알고리듬을 취하여 입력의 샘플링속도, 프로세서의 수, 그리고 주어진 입력에 대한 출력의 지연에 있어 최적인 Cyclo-static 스케줄러를 생성하여 각 프로세서간의 연결선이 최소가 되도록 스케줄을 변환한다. 회로도 생성 단계에서는 이 변환된 스케줄러로부터 미리 정의된 두 가지 형태의 프로세서 구조를 이용하여 그것을 구성하고 있는 레지스터 및 멀티플렉서의 할당을 행하고 제어신호를 포함한 완전한 회로도를 생성한다, 이렇게 생성된 회로도는 기존의 실리콘 컴파일러를 이용하여 VLSI 레이아웃으로 용이하게 변환 될 수 있다.

• 한국컴퓨터정보학회논문지
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• 제6권1호
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• pp.7-13
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• 2001

VLSI의 집적도가 증가함에 따라 설계와 제조과정에서 기존의 논리 테스트 방법으로는 검출하기 어려운 고장들이 발생하고 있다. 최근에는 이러한 고장을 검출하기 위한IDDQ 테스팅 방법의 중요성이 증대되고 있다. 본 논문에서는 CMOS 회로내에서 IDDQ 값을 검사하여 고장의 유무를 검사하는 전류 테스팅 기법에 사용될 수 있는 새로운 전류감지기를 제안한다. 본 논문에서 제안된 전류감지기는 자기저항 소자 MR 전류감지기, 레벨변환기, 비교기로 구성되어 있으며 자동으로 고장을 검출할 수 있다.

• 전자공학회지
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• 제25권5호
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• 대한전자공학회논문지
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• 제24권4호
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• pp.708-712
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• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• 전자공학회논문지A
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• 제29A권1호
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• pp.48-59
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• 1992

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.

• 전자공학회논문지A
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• 제30A권11호
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.