• Electrical & Electronic Materials
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• v.7 no.2
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• pp.107-116
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• 1994

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performances of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize deviations of device characteristics. In this paper, we used one-dimensional process simulator, SUPREM-II, and two dimensional device simulator, MINIMOS 4.0 in order to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derived the dependence relations between process parameters and device characteristics. Here, we have suggested a method to extract process parameters from design trend curve(DTC) obtained by these dependence relations. And we have discussed short channel effects and device limitations by scaling down MOSFET dimensions.

• The KIPS Transactions:PartC
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• v.8C no.2
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• pp.141-154
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• 2001

MOBAS는 규칙적인 모듈로 구성되어 있어 확장이 용이하며, VLSI 구현 시 고집적화 할 수 있고, 각 모듈간에 동기를 맞추기 쉬울 뿐 아니라, 단일 종류의 칩으로 중앙 스위치 구조를 구성할 수 있다. Modified MOBAS(Multicast Output Buffered ATM Switch)는 MOBAS와 유사한 구조를 가지지만 스위치 모듈(SM : Switch Module)의 구조에서 차이를 보이며 적은 스위치소자(SWE : Switch Element)를 사용한다. 위성 통신에서 스위치의 크기뿐 아니라 고장감내 특성도 스위치를 디자인하는데 필요한 중요한 요소이다. 본 논문에서는 Modified MOBAS의 고장 특성을 분석하고 이에 적합한 Detection 기법 및 Location 기법을 제안하였다. 또한 스위치 모듈구조를 변형하여 Modified MOBAS에 비해 약간의 스위치 소자를 더 사용하지만 MOBAS에 비해서는 적은 스위치 소자를 사용할 뿐 아니라, MOBAS와 같이 단일 고장 하에서 성능의 저하가 거의 없다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.1
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• pp.50-58
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• 2003

Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.133-142
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• 2012

In this paper, we propose and implement a high-speed algorithm for CGH that is to calculate digital hologram by modeling the interference phenomenon for tow lights. This algorithm changes the computation equations into a parallel-computable ones and implements it with a structure consisting of two kinds of cells (initial calculation cell, and update calculation cell). The parallel computation algorithm is to get the rest hologram pixels concurrently after calculation the first hologram column. Here, the initial calculation cells compute the first column of the hologram and the update calculation cells compute the rest of the hologram. The two kinds of cells performs a pipeline operation to complete the operations of the two cells at the same time. A CGH calculator to compute the hole hologram for a light source is structured by arranging the two kinds of cells. Results from simulation showed that the maximum operation frequency is about 215MHz. So, experiments are performed by setting this frequency and the same environments as the method showing the best performance. As the results, the proposed one could complete the computation of 81.75 CGH frames per second, while the previous method computes 62.9 CGH frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.