• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2935-2937
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• 1999

The human has recognizable part of body such as a fingerprint, a crimson, a blood vessel. This part has been investigated constantly, its confidence for personal recognition is high. In spite of specialized part of human body, a lip print recognition is developed less than the other physical attribute that is a fingerprint. a voice pattern, a retinal blood-vessel pattern, or a facial recognition. This paper is to implement hardware for lip print recognition system using VHDL.

• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.250-252
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• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.173-176
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• 2000

본 논문은 VHDL을 이용하여 1997년 국제 표준안으로 제정된 MPEG-2 AAC 복호화기의 각 모듈을 구현하였다. AAC 복호화기는 허프만 복호화, 역양자화, 고해상도 필터뱅크 등의 도구들이 필수적으로 사용된다. AAC 복호화기의 실시간 구현을 위해 각 도구들의 알고리즘을 분석하고, 하드웨어 개발에 알맞게 최적화하여 고속화와 적은 메모리를 사용하여 효율적으로 구현하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.1
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• pp.45-56
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• 1997

본 논문에서는, 무선 통신시스템에 적용 가능한 (255,215) BCH부호의 효율적인 복호 알고리즘을 제안하고, 이를 이용하여 5중 에러 정정 부호기 및 복호기를 설계하였다. peterson의 복호기보다 곱셈기, X-or 게이트의 수가 현저히 줄어들었을 뿐만 아니라 역원계산기가 필요 없음이 입증되었고, VHDL을 사용한 컴퓨터 시뮬레이션을 통해서 그 타당성을 검증하였다.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.5
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• pp.354-360
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• 2003

For the convenient use of high performance microprocessor in motor control, peripheral devices are needed for converting its control signals to compatible ones for motor drive. Customized devices are not plentiful far these purposes and their functions do not usually satisfied designers specification. The designers used to implement these functions on FPGA or CPLD using hardware description language. Then, in this case unessential programs are needed for control the peripherals. In this paper, a unified device model that links peripheral devices, including especially the pulse width modulation controller and the quadrature encoder interface device, to an interrupt controller is proposed. Advanced functions of peripherals could be achieved by this model and unessential programs can be simplified. Block diagrams and flowcharts are presented to illustrate the advanced functions. This unified device was designed using VHDL. The simulation results were presented to demonstrate the effectiveness of the proposed scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.398-402
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• 1999

본 논문에서는 MCM기술을 사용한 ATM용 Switching칩을 구현하고, 그 기능을 검증하였다. Switching칩의 MCM구현을 위해 기능 검증 및 상용화가 이루어진 기존 칩들의 VHDL코드를 이용하여 패키지 모델을 생성하였고, 칩의 검증은 VHDL 테스트벡터를 생성하고, 입ㆍ출력 값을 얻었다. 얻은 입력 데이터를 칩 테스트장비에 입력하여 구현된 칩에 넣고 나오는 출력을 벡터 시뮬레이션을 통해 얻은 결과 값과 비교하였다. 다양한 기능의 검증을 위하여 3가지 패턴의 벡터를 생성, 그 성능을 검증하였다. 본 연구에서 생성된 테스트 벡터는 썬 웍스테이션 상에서 Synopsys사의 툴인 vhdl analyzer와 vhdl debugger를 이용하여 simulation하였고, 각 벡터들의 입출력을 텍스트로 얻었다. 그리고 칩의 기능 시험을 위하여 일반적으로 사용되는 Trillium 장비를 사용하였다. 본 연구를 통하여 MCM후에 생성된 벡터의 입ㆍ출력 값과 테스트장비로부터 얻은 출력이 여러 기능들에 대하여 일치됨을 알았다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.26-35
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• 1997

In this paper, a VHDL implementation method for the internet protocol (IP) placed on top of ATM, so called IP over ATM, is presented. The proposed implementation method employs a parallel processing architecture to reduce the processing time and offers 155.52Mbps (STM-1) interface with the full-duplex mode for the ATM-based network. Furthermore, in order to minimize the search time for the table look-up, a LANCAM-based structure combining the routing table with the ATMARP table is proposed. The VHDL simulation results show that this proposed method can transmit (receive) at 155.52Mbps with delays of 48.5 clocks (29.5clocks).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.149-157
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• 1994

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.56-61
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• 2000

Silicon semiconductor technology agrees that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduces verification time. This Paper describes the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.