• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.289-292
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• 2000

This paper proposes a new FIR fillet architecture for the spectral shaping filter used in the transmitter and the receiver for QAM-VDSL modem. This architecture reduced the hardware property and the power consumption. We derive algorithms for reducing the number of multipliers and the memory architecture for reducing the power consumption. The proposed filter has been implemented using VHDL and performed functional simulation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.100-103
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• 2000

In this paper, we designed the equalizer optimized for VDSL modem chip using QAM method. The equalizer is capable of variable constellation. The equalizer was coded using VHDL and the logic simulation was performed. The test vector were generated based on the channel environments using MATLAB.

• Proceedings of the IEEK Conference
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• summer
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• pp.15-18
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• 2004

In this paper we present a linear discrete bit-loading algorithm that maximizes the transmit bit rate using the channel informations to optimize the performance of the very high-speed digital subscriber line(VDSL) system. It will be useful under the constraint of a maximum transmit power for each user. When the level of crosstalk is high, the power allocation of a user changes the noise experienced by the other users in the same binder. In this case, the performance of DSL modems can be improved by jointly considering the bit and power allocation of all users.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• TTA Journal
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• s.87
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• pp.102-107
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• 2003

• TTA Journal
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• s.87
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• pp.108-119
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• 2003

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.229-232
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• 2001

This paper has analyzed an architecture of DSLAM, system software Architecture, an external interface of DSLAM module, Message transfer of each task. Also in this paper, message and structures between SNMP Agent and each internal board are defined, and from the defined messages and data structures, message processing between boards is designed and implemented

• TTA Journal
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• s.80
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• pp.119-126
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• 2002

• TTA Journal
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• s.59
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• pp.59-66
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• 1998

• TTA Journal
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• s.87
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• pp.86-93
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• 2003