• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.470-475
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• 2015

This paper presents a wideband Current-Reused Voltage Controlled Oscillator (VCO) with 2-Step Automatic Amplitude Calibration (AAC). Tuning range of the proposed VCO is from 1.95 GHz to 3.15 GHz. The mismatch of differential voltage is within 0.6 %. At 2.423 GHz, the phase noise is -116.3 dBc/Hz at the 1 MHz offset frequency with the current consumption of 2.6 mA. The VCO is implemented $0.13{\mu}m$ CMOS technology. The layout size is $720{\times}580{\mu}m^2$.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.983-984
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• 2006

Multi-band VCO with fast response adaptive frequency calibration (AFC) technique is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators for 802.11a/b/g WLAN applications. To linearize its frequency-voltage gain, optimized multiple MOS varactor biasing technique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched-capacitor bank is used and a wide-range digital logic quadricorrelator is implemented for fast frequency detector.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.17-22
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• 2006

CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.87-93
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• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.