• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.132-139
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• 2002

This paper describes a supply voltage detector and SRAM write driver circuit which dissipates small power. The supply voltage detector generates high signal when supply voltage is higher than reference voltage, but low signal when supply voltage is lower than reference voltage. The write driver utilizes two same-sized drivers to reduce operating current in the write cycle. In the case of lower supply voltage comparing to Vcc, both drivers are active the same as conventional write driver, while in the case of high Vcc only one of two drivers are active so as to deliver the half of the current. As a result of simulation using 0.6${\mu}{\textrm}{m}$ 3.3v/5v, CMOS model parameter, the proposed SRAM scheme shows a 22.6% power reduction and 12.7% PDP reduction at Vcc=3.3V, compared to the conventional one.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.69-72
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• 2000

This paper describes an SRAM write driver circuit which dissipates small power. The write driver utilizes a dual sized transistor structure to reduce operating current in the write cycle. In the case of higher voltage comparing to Vcc, only one transistor is active, while in the case of low Vcc two transistors are active so as to deliver the current twice. Thus though with the high voltage operation, the power consumption is reduced with keeping the speed in a given specification. Simulation results have verified the functionality of the new circuit and write power is reduced by 7 % per bit.