• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.1-8
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• 1998

In this paper, we designed a low power 8bit ELM adder with static CMOS and hybrid logic styles on a chip. The designed 8bit ELM adder with both logic styles was fabricated in a 0.8$\mu\textrm{m}$ single-poly double-metal, LG CMOS process and tested. Hybrid logic style consists of CCPL(Combinative Complementary Pass-transistor Logic), Wang's XOR gate and static CMOS for critical path which determines the speed of ELM adder. As a result of chip test, the ELM adder with hybrid logic style is superior to the one with static CMOS by 9.29% in power consumption, 14.9% in delay time and 22.8% in PDP(Power Delay Product) at 5.0V supply voltage, respectively.

• Archives of Pharmacal Research
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• v.27 no.2
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• pp.254-258
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• 2004

The purpose of this study was to investigate the pharmacokinetic alteration of diltiazem and its main metabolite, deacetyldiltiazem, after oral administration of diltiazem in rabbits with or with-out cimetidine co-administration. The area under the plasma concentration-time curve (AUC) of diltiazem was significantly elevated in rabbits pretreated with cimetidine, suggesting that the oral clearance, an index of intrinsic clearance, may be decreased by the cimetidine treatment. Consistent with the increased AUC by the treatment, peak plasma concentration ($C_{max}$) for diltiazem was also elevated. Apparent volume of distribution normalized by the bioavailability (($V_{d}$/F) of diltiazem increased sigrificantly in rabbits pretreated with cimetidine increased. Taken together with the fact that the first pass metabolism for diltiazem is the primary determinant for the oral bioavailability, these observations indicate that increases in the oral clearance and (($V_{d}$/F may be a manifestation of the decreased first pass metabolism. Consistent with the hypothesis, the AUC of deacetyldiltiazem was significantly decreased in rabbits with cimetidine treatment. Ratio of deacetyldiltiazem to total diltiazem in the plasma was significantly decreased in rabbits with cimetidine treatment. These observations suggested that the metabolism of diltiazem to deacetyldiltiazem was reduced by cimetidine treatment and that the dosage of diltiazem should be adjusted when the drug is co-administered chronically with cimetidine in a clinical setting.

• Journal of Surface Science and Engineering
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• v.13 no.4
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• pp.221-227
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• 1980

When anodizing the Al in the acid electrolyte, it is well known that the parallel pores grow continuously perpendicular to the surface. This fact can be used for the manufacturing of the porous membrane, if thc pores pass through the anodized foil. Anodizing both surfaces of the Al-foil spontaneously in 20$^{\circ}C$, 2% oxalic acid under tile potentiostatic condition, it is found that the harrier layer remaining in the midst of the foil finally disappears and thc pores pass through the foil. And examined the porous structure change when the voltage is changed during the anodizing treatment. From the result, it is revealed that the new pores and cell grow, adjusting themselves to the final voltage. The characteristic of the porous membrane is greatly dependent upon the diameter of the pore and the cell. So studied the relationship between the voltage and the diameter of the pore and the cell quantitatively with the aid of field-assisted dissolution concept. And derived the following two equation, Pi = 8.32Vi, Ci = 26.80Vi. These equations are in good accord with the experimental data above 30V, but do not accord nuder 30V.

• Journal of IKEEE
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• v.15 no.1
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• pp.57-63
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• 2011

This paper presents a tunable band pass filter (BPF) for multi bio-signal detection. The bandwidth can be controlled by the bias current of transconductance (gm), while conventional BPF exploited switchable capacitor array for band selection. With this design technique, the die area of proposed BPF reduced to at least one tenth the area of conventional design. The simulation results show the high cut-off frequency tuning range of from 100Hz to 1Khz. The circuit was implemented with a 0.18um CMOS standard technology. Total current consumption is 1uA at the supply voltage of 1V with sub-threshold design technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.201-206
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• 2015

A new electronically stopband tunable filter is proposed with three-input single-output using Operational Transconductance Amplifier (OTA) in this paper. The proposed filter provides band pass, low pass and high pass multifunctional responses. Centre frequency ($f_c$) and quality factor (Q) of the realized filters could independently tuned without disturbing each other. Various network sensitivity and non-ideal characteristic analysis are done to check the sensitivity and parasitic effect of different circuit parameters. The CMOS realization of filter is done with 1.8V-0.18um process parameters and HSPICE simulation results are presented to assert the presented theory.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2002.05a
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• pp.177-180
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• 2002

The effects of pressing temperatures on the formability and the microstructural evolution during equal channel angular pressing (ECAP) of lamellar Ti-6Al-4V alloy were investigated in this study. ECAP above isothermally 600$^{\circ}C$ was successful without producing any noticeable segments at the specimen surfaces after a single pass of pressing. After 4 passes of ECA pressing, lamellar microstructures were significantly refined revealing equiaxed grains of 0.3$\mu\textrm{m}$ in diameter consisting of high angle grain boundaries. Also these ultrafine grains were relatively stable with little grain growth when annealed up to 600$^{\circ}C$ for 1hour.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• ETRI Journal
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• v.39 no.3
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).