• Title/Summary/Keyword: V-mask

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Influence of Wet Chemistry Damage on the Electrical and Structural Properties in the Wet Chemistry-Assisted Nanopatterned Ohmic Electrode (Wet chemistry damage가 Nanopatterned p-ohmic electrode의 전기적/구조적 특성에 미치는 영향)

  • Lee, Young-Min;Nam, Hyo-Duk;Jang, Ja-Soon;Kim, Sang-Mook;Baek, Jong-Hyub
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.150-150
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    • 2008
  • 본 연구에서는 Wet chemistry damage가 Nanopatterned p-ohmic electrode에 미치는 영향을 연구하였다. Nanopattern은 Metal clustering을 이용하여, P-GaN와 Ohmic형성에 유리한 Pd을 50$\AA$ 적층한 후 Rapid Thermal Annealing방법으로 $850^{\circ}C$, $N_2$분위기에서 3min열처리를 하여 Pd Clustering mask 를 제작하였다. Wet etching은 $85^{\circ}C$, $H_3PO_4$조건에서 시간에 따라 Sample을 Dipping하는 방법으로 시행하였다 Ohmic test를 위해서 Circular - Transmission line Model 방법을 이용하였으며, Atomic Force Microscopy과 Parameter Analyzer로 Nanopatterned GaN surface위에 형성된 Ni/ Au Contact에서의 전기적 분석과, 표면구조분석을 시행하였다. AFM결과 Wet처리시간에 따라서 Etching형상 및 Etch rate이 영향을 받는 것이 확인되었고, Ohmic test에서 Wet chemistry처리에 의한 Tunneling parameter와 Schottky Barrier Height가 크게 증/감함을 관찰하였다. 이러한 결과들은 Wet처리에 의해서 발생된 Defect가 GaN의 표면과 하부에서 발생되며, Deep acceptor trap 및 transfer거동과 밀접한 관련이 있음을 확인 할 수 있었다. 보다 자세한 Transport 및 Wet chemical처리영향에 관한 형성 Mechanism은 후에 I-V-T, I-V, C-V, AFM결과 들을 활용하여 발표할 예정이다.

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Micropattern generation by holographic lithography and fabrication of quantum wire array by MOCVD (홀로그래픽 리소그래피에 의한 미세패턴 형성과 MOCVD에 의한 양자세선 어레이의 제작)

  • Kim, Tae-Geun;Cho, Sung-Woo;Im, Hyun-Sik;Kim, Young;Kim, Moo-Sung;Park, Jung-Ho;Min, Suk-Ki
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.6
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    • pp.114-119
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    • 1996
  • The use of holographic interference lithography and removal techniques to corrugate GaAs substrate have been studied. The periodic photoresist structure, which serves as a protective mask during etching, is holographically prepared. Subsequently periodic V-grooved pattern is formed on the GaAs substrate by conventional a H$_{2}$SO$_{4}$-H$_{2}$O$_{2}$-H$_{2}$O wet etching. The linewidth of a GaAs pattern is about 0.4$\mu$m and the depth is 0.5$\mu$m A quantum wires(QWRs) array is well formed on the V-grooved substrate by MOCVD (metalorganic chemical vapor deposition) growth of GaAs/Al$_{0.5}$Ga$_{0.5}$As (50$\AA$/300$\AA$) quantum wells. The formation of QWR array is confirmed by the temperature dependent photoluminescence (PL) measurement. The intensive PL peak with a FWHM of 6meV at 21K shows the high quality of the QWR array.

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Microfabrication of Submicron-size Hole on the Silicon Substrate using ICP etching

  • Lee, J.W.;Kim, J.W.;Jung, M.Y.;Kim, D.W.;Park, S.S.
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.79-79
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    • 1999
  • The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

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High Density Inductively Coupled Plasma Etching of III-V Semiconductors in BCI3Ne Chemistry (BCI3Ne 혼합가스를 이용한 III-V 반도체의 고밀도 유도결합 플라즈마 식각)

  • 백인규;임완태;이제원;조관식
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.12S
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    • pp.1187-1194
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    • 2003
  • A BCl$_3$/Ne plasma chemistry was used to etch Ga-based (GaAs, AIGaAs, GaSb) and In-based (InGaP, InP, InAs and InGaAsP) compound semiconductors in a Planar Inductively Coupled Plasma (ICP) reactor. The addition of the Ne instead of Ar can minimize electrical and optical damage during dry etching of III-V semiconductors due to its light mass compared to that of Ar All of the materials exhibited a maximum etch rate at BCl$_3$ to Ne ratios of 0.25-0.5. Under all conditions, the Ga-based materials etched at significantly higher rates than the In-based materials, due to relatively high volatilities of their trichloride etch products (boiling point CaCl$_3$ : 201 $^{\circ}C$, AsCl$_3$ : 130 $^{\circ}C$, PCl$_3$: 76 $^{\circ}C$) compared to InCl$_3$ (boiling point : 600 $^{\circ}C$). We obtained low root-mean-square(RMS) roughness of the etched sulfate of both AIGaAs and GaAs, which is quite comparable to the unetched control samples. Excellent etch anisotropy ( > 85$^{\circ}$) of the GaAs and AIGaAs in our PICP BCl$_3$/Ne etching relies on some degree of sidewall passivation by redeposition of etch products and photoresist from the mask. However, the surfaces of In-based materials are somewhat degraded during the BCl$_3$/Ne etching due to the low volatility of InCl$_{x}$./.

Study on Pressure-dependent Growth Rate of Catalyst-free and Mask-free Heteroepitaxial GaN Nano- and Micro-rods on Si (111) Substrates with the Various V/III Molar Ratios Grown by MOVPE

  • Ko, Suk-Min;Kim, Je-Hyung;Ko, Young-Ho;Chang, Yun-Hee;Kim, Yong-Hyun;Yoon, Jong-Moon;Lee, Jeong-Yong;Cho, Yong-Hoon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.180-180
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    • 2012
  • Heteroepitaxial GaN nano- and micro-rods (NMRs) are one of the most promising structures for high performance optoelectronic devices such as light emitting diodes, lasers, solar cells integrated with Si-based electric circuits due to their low dislocation density and high surface to volume ratio. However, heteroepitaxial GaN NMRs growth using a metal-organic vapor phase epitaxy (MOVPE) machine is not easy due to their long surface diffusion length at high growth temperature of MOVPE above $1000^{\circ}C$. Recently some research groups reported the fabrication of the heteroepitaxial GaN NMRs by using MOVPE with vapor-liquid-solid (VLS) technique assisted by metal catalyst. However, in the case of the VLS technique, metal catalysts may act as impurities, and the GaN NMRs produced in this mathod have poor directionallity. We have successfully grown the vertically well aligned GaN NMRs on Si (111) substrate by means of self-catalystic growth methods with pulsed-flow injection of precursors. To grow the GaN NMRs with high aspect ratio, we veried the growth conditions such as the growth temperature, reactor pressure, and V/III molar ratio. We confirmed that the surface morphology of GaN was strongly influenced by the surface diffusion of Ga and N adatoms related to the surrounding environment during growth, and we carried out theoretical studies about the relation between the reactor pressure and the growth rate of GaN NMRs. From these results, we successfully explained the growth mechanism of catalyst-free and mask-free heteroepitaxial GaN NMRs on Si (111) substrates. Detailed experimental results will be discussed.

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Characterization of GaN epitaxial layer grown on nano-patterned Si(111) substrate using Pt metal-mask (Pt 금속마스크를 이용하여 제작한 나노패턴 Si(111) 기판위에 성장한 GaN 박막 특성)

  • Kim, Jong-Ock;Lim, Kee-Young
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.3
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    • pp.67-71
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    • 2014
  • An attempt to grow high quality GaN on silicon substrate using metal organic chemical vapor deposition (MOCVD), herein GaN epitaxial layers were grown on various Si(111) substrates. Thin Platinum layer was deposited on Si(111) substrate using sputtering, followed by thermal annealing to form Pt nano-clusters which act as masking layer during dry-etched with inductively coupled plasma-reactive ion etching to generate nano-patterned Si(111) substrate. In addition, micro-patterned Si(111) substrate with circle shape was also fabricated by using conventional photo-lithography technique. GaN epitaxial layers were subsequently grown on micro-, nano-patterned and conventional Si (111) substrate under identical growth conditions for comparison. The GaN layer grown on nano-patterned Si (111) substrate shows the lowest crack density with mirror-like surface morphology. The FWHM values of XRD rocking curve measured from symmetry (002) and asymmetry (102) planes are 576 arcsec and 828 arcsec, respectively. To corroborate an enhancement of the growth quality, the FWHM value achieved from the photoluminescence spectra also shows the lowest value (46.5 meV) as compare to other grown samples.

Building change detection in high spatial resolution images using deep learning and graph model (딥러닝과 그래프 모델을 활용한 고해상도 영상의 건물 변화탐지)

  • Park, Seula;Song, Ahram
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.40 no.3
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    • pp.227-237
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    • 2022
  • The most critical factors for detecting changes in very high-resolution satellite images are building positional inconsistencies and relief displacements caused by satellite side-view. To resolve the above problems, additional processing using a digital elevation model and deep learning approach have been proposed. Unfortunately, these approaches are not sufficiently effective in solving these problems. This study proposed a change detection method that considers both positional and topology information of buildings. Mask R-CNN (Region-based Convolutional Neural Network) was trained on a SpaceNet building detection v2 dataset, and the central points of each building were extracted as building nodes. Then, triangulated irregular network graphs were created on building nodes from temporal images. To extract the area, where there is a structural difference between two graphs, a change index reflecting the similarity of the graphs and differences in the location of building nodes was proposed. Finally, newly changed or deleted buildings were detected by comparing the two graphs. Three pairs of test sites were selected to evaluate the proposed method's effectiveness, and the results showed that changed buildings were detected in the case of side-view satellite images with building positional inconsistencies.

Characteristics of Double-junction of High-$\textrm{T}_{c}$ Superconducting $\textrm{YBa}_{2}\textrm{Cu}_{3}\textrm{O}_{7-x}$ Step-edge Junctions (고온 초전도 $\textrm{YBa}_{2}\textrm{Cu}_{3}\textrm{O}_{7-x}$ 계단형 모서리 접합의 이중접합 특성)

  • Hwang, Jun-Sik;Seong, Geon-Yong;Gang, Gwang-Yong;Yun, Sun-Gil;Lee, Gwang-Ryeol
    • Korean Journal of Materials Research
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    • v.9 no.1
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    • pp.86-91
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    • 1999
  • We have fabricated high-$\textrm{T}_c$ superconducting $\textrm{YBa}_{2}\textrm{Cu}_{3}\textrm{O}_{7-x}$(YBCO) grain boundary junctions at a step-edge on (001) $\textrm{SrTiO}_3$(STO) substrates. A diamond-like carbon (DLC) film grown by plasma enhanced chemical vapor deposition were used as an ion milling mask to make steps on the STO (100) single crystal and was removed by an oxygen reactive ion etch process. The c-axis oriented YBCO and TO thin films were deposited epitaxially on the STO substrate with a step-edge by pulsed laser deposition. The grain boundary junctions were formed at the top and the bottom of the step. The junctions worked at temperatures above 77 K, and had I\ulcornerR\ulcorner products of 7.5mV at 16K and 0.3 mV at 77K, respectively. The I-V characteristics of these junctions showed the shape of the two noisy resistively shunted junction model.

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The Simulation of Selective Emitter Formation for Crystalline Silicon Solar Cell by Growing Thermal Oxide (Thermal oxidation을 이용한 결정질 실리콘 태양전지의 selective emitter 형성 방법에 대한 simulation)

  • Choe, Yonghyon;Son, Hyukjoo;Lee, Inji;Park, Jeagun;Park, Yonghwan
    • 한국신재생에너지학회:학술대회논문집
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    • 2010.11a
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    • pp.53.1-53.1
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    • 2010
  • 결정질 실리콘 태양전지의 효율을 향상시키기 위하여 수광면에 서로 다른 도핑농도를 가지는 고농도 도핑영역과 저농도 도핑영역으로 이루어진 emitter를 형성하는 것이 요구되며 이를 selective emitter라 칭한다. Selective emitter를 형성하면 고농도 도핑영역에서 금속전극과 저항 접촉이 잘 형성되기 때문에 직렬 저항이 최소화되고 저농도 도핑영역에서는 전하 재결합의 감소로 인하여 태양전지의 변환효율이 상승하는 이점이 있다. Selective emitter의 형성방법은 이미 다양한 방법이 제안되고 있으나, 본 연구에서는 기존에 제시된 방법과는 다르게 열산화 시 dopant redistribution에 의한 Boron depletion 현상을 이용하여 selective emitter를 형성하는 방법을 제안하였고, 이를 Simulation을 통하여 검증하였다. 초기 emitter 확산 후 junction depth는 0.478um, 면저항은 $104.2{\Omega}/sq.$ 이었으며, nitride masking layer 두께는 0.3um로 설정하였다. $1100^{\circ}C$에서 30분간 습식산화 공정을 거친 후 nitride mask가 있는 부분의 junction depth는 1.48um, 면저항은 $89.1{\Omega}/sq$의 값을 보였고, 산화막이 형성된 부분의 junction depth는 1.16um, 면저항은 $261.8{\Omega}/sq$의 값을 보였다. 위 조건의 구조를 가진 태양전지의 변환 효율은 19.28%의 값을 나타내었고 Voc, Jsc 및 fill factor는 각각 645.08mV, $36.26mA/cm^2$, 82.42%의 값을 보였다. 한편 일반적인 구조로 설정한 태양전지의 변환 효율, Voc, Isc 및 fill factor는 각각 18.73%, 644.86mV, $36.26mA/cm^2$, 80.09%의 값을 보였다.

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광전자소자의 응용을 위한 산화아연 나노로드의 패터닝 형성방법

  • Go, Yeong-Hwan;Yu, Jae-Su
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.97-97
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    • 2011
  • 산화아연 (ZnO)은 넓은 에너지 밴드갭 (~3.37 eV), 큰 엑시톤 결합 에너지 (~60 meV) 그리고 높은 전자 이동도 (bulk~300 $cm^2Vs^{-1}$, single nanowire~1000 $cm^2Vs^{-1}$)를 갖고 있어, 광전자 소자 및 반도체소자 응용에 매우 널리 사용되고 있다. 특히, 산화아연 나노로드(ZnO nanorod)는 1차원 나노구조로써 더욱 향상된 전자 이동도와 캐리어의 direct path way를 제공하여 차세대 광전자소자 및 태양광 소자의 응용에 대한 연구가 매우 활발하게 이루어지고 있다. 한편, 이러한 산화아연 나노로드를 성장시키기 위하여 VLS (vapor-liquid-solid), 졸-겔 공정(sol-gel process), 수열합성(hydrothermal synthesis), 전기증착(electrodeposition)등 다양한 방법이 보고되었지만, 이러한 산화아연 나노로드의 성장방법은 실제적인 소자응용을 위한 패터닝 형성에 대하여 제약을 받는 문제점이 있다. 이들 중에서 수열합성법과 전극증착법은 ZnO 또는 AZO (Al doped ZnO) seed 층 표면과 성장용액의 화학반응에 의해서 선택적으로 산화아연 나노로드를 성장시킬 수 있다. 이에 본 연구에서는, 광전자소자의 응용을 위한 간단한 패터닝 공정을 위해, 산화인듐주석(ITO) 박막이 증착된 유리기판(glass substrate)위에 수열합성법과 전극증착법을 이용하여 산화아연 나노로드를 선택적으로 성장시켰다. 실험을 위해, ITO glass 위에 RF magnetron 스퍼터를 사용하여 AZO seed 층을 metal shadow mask를 이용하여 패터닝을 형성한 후, 질산아연과 헥사메틸렌테트라아민으로 혼합된 용액에 $85^{\circ}C$ 온도를 유지하여, 패터닝이 형성된 샘플에 전압을 인가하여 성장시켰다. 나노구조 분석을 위해, 전계주사현미경을 이용하여 수열합성법과 전기증착법에 의한 패터닝된 산화아연 나노로드를 비교하여 관찰하였다.

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