• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.301-310
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• 2017

Quantum-dot cellular automata(QCA) is an alternative technology for implementing various computation, high performance, and low power consumption digital circuits at nano scale. In this paper, we propose a new universal gate in QCA. By using the universal gate, we propose a novel XOR gate which is reduced time/hardware complexity. The universal gate can be used to construct all other basic logic gates. Meanwhile, the proposed universal gate is designed by basic cells and a rotated cell. The rotated cell of the proposed universal gate is located at the central of 3-input majority gate structure. In this paper, we propose an XOR gate using three universal gates, although more than five 3-input majority gates are used to design an XOR gate using the 3-input majority gate. The proposed XOR gate is superior to the conventional XOR gate in terms of the total area and the consumed clock because the number of gates are reduced.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of the Korean Society for Precision Engineering
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• v.12 no.12
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• pp.109-119
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• 1995

A driveline incorporating universal joints when driving through an angle can excite various components in a vehicle with second order excitation of torsional and bending vibrations, being transmitted either audibly(noise), or physically(vibration). For a certain range of vehicle dpeed noises can be radiated from the cab wall, in which resonances occur by the excitations transmitted from the driveline as a vibration source. In this paper, the excitation mechanism of cab noises is studied especially for the vehicle speed range of 65 .approx. 75 km/h through the simulation for torsional vibrations of the driveline and for bending vibrations of the cab of an 11 Ton grade Cargo Truck, and verified additionally by vibration and noise measurements. As a result, it is found that the uncomfortable noises in the cab are caused mainly by the abrupt increase of the joint angle of driveline near the axle differential resulted from the excessive clearance alignment of the leaf spring gate.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.87-96
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• 2021

Quantum computers will be a game-changer in various fields, such as cryptography and new materials. Quantum computer is quite different from the classical computer by using quantum-mechanical phenomena, such as superposition, entanglement, and interference. The main components of a quantum computer can be divided into quantum-algorithm, quantum-classical control interface, and quantum processor. Universal quantum computing, which can be applied in various industries, is expected to have more than millions of qubits with high enough gate accuracy. Currently, It uses general-purpose electronic equipment, which is placed in a rack, at room temperature to make electronic signals that control qubits. However, implementing a universal quantum computer with a low error rate requires a lot of qubits demands the change of the current control system to be an integrated and miniaturized system that can be operated at low temperatures. In this study, we explore the fundamental units of the control system, describe the problems and alternatives of the current control system, and discuss a future quantum control system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.85-89
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• 2003

Many single-stage PFC(power-facto.-correction) ACHC converters suffer from the high link voltage at high input voltage and light load condition. In this paper, to suppress the link voltage, a novel high power factor high efficiency PFC AC/DC converter is proposed using the single controller which generates two gate signals so that one of them is used far gate signal of the flyback DC/DC converter switch and the other is applied to the Boost PFC stage. A 130w prototype for LCD monitor adapter with universal input $(90-265V_{rms})$ and 19.5V 6.7A output is implemented to verify the operational principles and performances. The experimental results show that the maximum link voltage stress is about 450V at 270Vac input voltage. Moreover, efficiency and power factor are over $84\%$ and 0.95, respectively, under the full load condition.

• Journal of the Korean Magnetics Society
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• v.16 no.1
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• pp.84-87
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• 2006

We suggest a procedure entangling two spin-1/2 particles at distant positions such that they cannot be directly entangled via local interaction. An already entangled pair is used to transfer the entanglement to another pair of particles by way of interaction. This scheme of nonlocal generation of entanglement can be used in the construction of a two-qubit universal gate.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.318-321
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• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.6
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• pp.110-116
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• 1994

In this research, the tensile strength of molded parts and pressure distribution were analyzed to study the cavity filling stage and packing stage in injection molding. The measurement of cavity pressure was obtained by a data acquisition system with the installation of transducers in the cavity. Molded parts were tested by a universal testing machine to obtain the tensile strength. For the experimental work, the tensile strength of molded parts increased with longer packing time and exact freezing time of the gate was obtained by a cavity pressure curve. In addition, the effect of packing did not occur and tensile strength was almost constant after early 1.5 sec of the freezing time of gate. Density tended to be higher about 0.2% due to a larger degree of mold temperature and melt temperature. Also, changing pressure in the cavity was effectively sensed. Thereafter, the possibility of the development of pattern recognition expert system was confirmed on the basis of the experimental results.