• Title/Summary/Keyword: Universal Serial Bus (USB)

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FPGA Design of LCD Drive Circuit using USB Interface (USB 인터페이스를 이용한 LCD 구동회로의 FPGA 설계)

  • Lee, Seung-Ho;Lee, Ju-Hyeon
    • The KIPS Transactions:PartA
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    • v.9A no.1
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    • pp.53-60
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    • 2002
  • This paper describes a Gray Mode Graphic STN LCD drive circuit using USB interface. The drive circuit using USB interface can highly transfer image data created under PC t LCD. Hence, the LCD drive circuit doesn't use microprocessor for the convenience of users. The proposed LCD drive circuit part have been verified by simulation and by ALTERA EPF10K10TC144-3 FPGA implementation in VHDL. The USB interface part have been programmed in MS-Visual C++ 6.0. The validity and efficiency of the proposed LCD drive circuit have been verified by test board. After comparing this LCD drive circuit to specify it was verified that the developed LCD drive circuit showed good performances, such as convenience of users, low cost.

Resource Management Scheme for Improvement of Reliability and Connectivity in wireless USB System (무선 USB 시스템에서 신뢰성과 연결성 향상을 위한 자원 관리 기법)

  • Kim, Jin-Woo;Jeong, Min-A;Lee, Seong Ro
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.11
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    • pp.1159-1166
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    • 2014
  • In this paper, a resource management scheme for enhancing the network connectivity and reliability in wireless USB system is proposed. Wireless USB protocol is suitable for the application that supports the real-time multimedia service in Ship Area Network since it supports high speed data transfer. However, the device's mobility is caused the dramatic change of link state and network topology, and is occurred the degradation of network performance. Therefore, a resource management scheme for wireless USB system is proposed in this paper. The proposed technique can intelligently treat the change of link state, and solve the degradation of network performance. The simulation results show that proposed protocol can enhance the throughput and delay performance by selecting relay device with better link state.

Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

  • Tan, Fern-Nee;Lee, Sheng Chyan
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.69-74
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    • 2013
  • In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

An Implementation of Mobile Gateway Based on Android Smartphone (안드로이드 스마트폰 기반의 모바일 게이트웨이 구현)

  • Lee, Donggeon;Lim, Jae-Hyun
    • Journal of Digital Convergence
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    • v.12 no.1
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    • pp.333-338
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    • 2014
  • Zigbee is a wireless communication technology optimized for WSN (Wireless Sensor Network) environment. A WSN gateway is used for node control and data transmission. However, a fixed-type gateway can restrict the flexibility of the WSN environment. A smartphone-mounted high-performance processor and Android OS can be easily used in a mobile WSN gateway. In this paper, we proposed a mobile WSN gateway based on Android smartphones. In the proposed system, a Zigbee sensor module is connected with a smartphone via USB (Universal Serial Bus) port. We also implemented an Android application for the mobile WSN gateway.

Broadband Active RF Attenuator with Maximun Attenuation of -110dBm (최대 -110dBm 감쇄기능을 제공하는 능동형 광대역 RF 감쇄기)

  • Paik, Junghoon
    • Journal of Broadcast Engineering
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    • v.22 no.5
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    • pp.665-670
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    • 2017
  • In this paper, we propose an implementation technology for an active attenuator with the maximum attenuation of -110dBm in the frequency band of 50MHz to 2,15GHz. It provides USB interface to connect to PC providing GUI that sets signal frequency and attenuation step of minimum 1dB. As it attenuates the input signal level down to -110dBm, circuit and equipment design technologies are applied to control both internal and external electro-magnetic noises.. Through the performance test, it is assured that it attenuates input signal level down to -110dBm for the input signal levels of -10 to -30dBm.

A QoS-aware Time slot allocation Algorithm for Distributed MAC in UWB Wireless Personal Area Networks (UWB 분산 제어기반 WPAN MAC 에서 QoS를 고려한 시간 슬롯 할당 알고리즘의 제안)

  • Park, Ji-Seon;Hur, Kyeong;Eom, Doo-Seop
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.263-264
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    • 2008
  • 고속 무선 PAN(Personal Area Networks)기술은 10m 이내의 짧은 거리에서 고속으로 대용량의 데이터를 전송하기 위한 기술로, 최근 무선 USB(Wireless Universal Serial Bus)나 HDTV(High Definition TV)와 같은 광대역 멀티미디어 응용 시장을 겨냥한 연구가 IEEE 802.15.3과 WiMedia를 중심으로 활발히 진행되고 있다. [1] 본 논문에서는 WiMedia Alliance에서 제안한 Distributed Medium Access Control (D-MAC)에서 다수 스트림의 QoS 요구를 만족시키는 신뢰성 있는 전송을 위해 데이터 시간 슬롯을 효율적으로 할당하는 알고리즘에 대해 연구하고자 한다.

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Quantitative Evaluation of Fabric Drape Using Image Analysis (화상처리기법을 활용한 천의 드레이프성의 정량적 평가방법)

  • Park, Chang-Kyu
    • Fashion & Textile Research Journal
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    • v.4 no.3
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    • pp.284-288
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    • 2002
  • In this research, a new quantitative fabric drape evaluation system has been developed using image processing technology. The purpose of this research is to get the more detailed information of fabric drapability quantitatively from digital images captured with a digital camera generally commercialized. The shape parameters of a 3-dimensional geometric drape model were defined as the number of nodes, frequency and amplitude. Also, various statistical information of drape shapes can be obtained using image processing technology and frequency analysis as well as traditional drape coefficients. Hardware system to capture drape images is simply composed of three parts including a digital USB (Universal Serial Bus) camera, a frame cover and a stand for camera to attach to traditional drape tester. The evaluation software coded with the MS Visual C++ is operated under the MS windows 9x above.

A Vision-based Electronic Chalk System by Using Infrared Light (적외선을 이용한 카메라 기반의 전자 분필 시스템)

  • Kim, Ji-Ae;Park, So-Yeon;Lee, Seon-A;Choe, Hye-Yeong;Lee, Ui-Cheol;Hwang, Min-Cheol
    • Proceedings of the Korean Society for Emotion and Sensibility Conference
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    • 2009.05a
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    • pp.249-252
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    • 2009
  • 본 연구는 화면전환 및 필기 등의 프레젠테이션을 편리하게 제어 할 수 있는 시스템을 구현하고자 한다. 카메라를 이용한 컴퓨터 비전 분야에서 주변의 조명 환경의 영향을 적게 받는 적외선을 이용한 연구가 활발하게 진행되고 있다. 제안하는 방법에서는 USB(Universal Serial Bus) 타입의 카메라를 적외선 환경에 맞게 개조하고, 이를 이용하여 적외선 LED(Light Emitting Diode)를 이용한 전자 분필 영상을 취득하여, 실시간으로 전자 분필의 위치를 검출한다. 검출된 영역은 사전에 사용자가 설정한 '필기 가능 영역'과 변형 함수에 기반하여, 실제 모니터 좌표로 사상되어 화면에 표시되게 된다. 제안하는 시스템은 저렴한 가격의 웹 캠과 적외선 조명 이외에는 별도의 장비가 필요하지 않으면서도, 대형 스크린을 터치 방식으로 활용할 수 있다는 장점을 가진다. 실험 결과, 계산된 모니터 좌표와 사용자가 의도한 위치간의 평균 RMS(Root Mean Square) 오차는 약 15픽셀로 나타나서, 글씨를 필기하고 화면의 특정 부분을 강조하기 위한 활용이 가능함을 확인할 수 있었다.

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A Study on JTAG Writer for multiple SoCs (다중 SoC를 지원하는 JTAG Writer에 관한 연구)

  • Ling-Li Piao;Young-Sup Roh
    • Proceedings of the Korea Information Processing Society Conference
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    • 2008.11a
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    • pp.810-813
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    • 2008
  • 본 논문에서 연구하고 구현된 JTAG(Joint Test Action Group) Writer는 하나의 SoC(System On a Chip)만 지원하도록 설계된 기존 제품의 단점을 보완할 수 있도록 각 SoC의 제조 회사에서 제공하는 BSDL(Boundary Scan Description Language)을 이용하여 여러 가지 SoC에 쉽게 사용할 수 있도록 모듈화 했다. 그리고 기존 제품들이 사용하고 있는 직렬 포트나 병렬 포트 대신 안정적이고 편리한 USB(Universal Serial Bus) 접속규격을 지원하도록 개선했다.

A Fully Synthesizable Bluetooth Baseband Module for a System-on-a-Chip

  • Chun, Ik-Jae;Kim, Bo-Gwan;Park, In-Cheol
    • ETRI Journal
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    • v.25 no.5
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    • pp.328-336
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    • 2003
  • Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

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