• Journal of Digital Contents Society
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• v.13 no.2
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• pp.169-176
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• 2012

This paper presents a parallel object-oriented programming (OOP) platform for efficient visualization of three-dimensional content in CUDA environments. For this purpose, this paper discusses the features and limitations in implementing C++ object-oriented codes using CUDA and proposes the solutions. Also, it presents how to implement a 3D parallel visualization platform based on the MVC (Model/View/Controller) design pattern. Also, it provides sample implementations for integral MLS (iMLS) and signed distance fields (SDFs) based on the Marching Cubes and Raytracing. The proposed approach enables GPU parallel processing only by implementing simple interfaces. Based on this, developers can expect general benefits that are common in general OOP techniques including abstractization and inheritance. Though I implemented only two specific samples in this paper, I expect my approach can be widely applied to general computer graphics problems.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.4
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• pp.470-475
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• 2014

Recently, smart phones are spread out as a universal mobile terminal equipment. Its provide USB interface to connect with various devices. Smart phones may be replaced with high priced monitoring equipments because of portability and mobility as its merit. In addition to that, the various sensor devices detecting surrounding environment of the radioactivity, sodium or electromagnetic waves have been announced. But the plug and play methods of sensor devices have some problem to connect smart phone with USB accessory device. We propose an integrated methodology that can connect smart phone with USB sensor devices and also, we realized USB accessory plug and play with one App that can collect measurement data through various sensor devices.

• Journal of Science and Technology Studies
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• v.1 no.2 s.2
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• pp.399-422
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• 2001

Models for human cognition currently discussed in cognitive science cannot be appropriate ones. The symbolic model of the traditional artificial intelligence works for reasoning and problem-solving tasks, but doesn't fit for pattern recognition such as letter/sound cognition. Connectionism shows the contrary phenomena to those of the traditional artificial intelligence. Connectionist systems has been shown to be very strong in the tasks of pattern recognition but weak in most of logical tasks. Brooks' situated action theory denies the. notion of representation which is presupposed in both the traditional artificial intelligence and connectionism and suggests a subsumption model which is based on perceptions coming from real world. However, situated action theory hasn't also been well applied to human cognition so far. In emphasizing those characteristics of models I refer those models 'left-brain model', 'right-brain model', and 'robot model' respectively. After I examine those models in terms of substantial items of cognitions- mental state, mental procedure, basic element of cognition, rule of cognition, appropriate level of analysis, architecture of cognition, I draw three arguments of embodiment. I suggest a way of unifying those existing models by examining their theoretical compatability which is found in those arguments.

• KIEAE Journal
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• v.7 no.6
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• pp.37-43
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• 2007

Discomfort glare is an important factor influencing appraisal for lighting environment. Unified Glare Rating (UGR) which has been proposed by CIE is one of the formula for evaluating discomfort glare. Position index is an important factor in the UGR formula. Position index was proposed by Guth in 1949. It has been used until present limiting upper visual field. Lower visual field has different sensation of brightness in comparing with upper visual field. Therefore, it is necessary to propose position index about lower visual field. The objective of this study is to investigate the brightness sensation in upper and lower visual field. First, the visual field was measured on the self-made Glare Tester. Second, luminance of the Borderline between Comfort and Discomfort (BCD) was measured on the glare Tester. Circular sources of brightness were located at various angular distances from the line of vision along five meridians, $0^{\circ}$, $45{\circ}$, $90{\circ}$, $-45{\circ}$, $-90{\circ}$. The size of the glare source is 0.0011sr. The luminance of the surrounding field, which extended over the entire visual field, was maintained $34ccd/m^2$. Ten subjects aged from 25 to 29 were participated in the experiment. The results show that the luminance of BCD on the line of vision is $4337cd/m^2$ and the glare sensation of the lower visual field is more sensitive than the upper visual field.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.6
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• pp.955-961
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• 2017

In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4B
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• pp.360-367
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• 2009

In this paper, we propose a design methodology of IEEE 802.11n MAC which aims to achieve the higher throughput of more than 100Mbps in downlink as measured at the MAC-SAP and present the implementation results of MAC using the proposed design methodology. With our proposed methodology, different from the conventional design flow which has the separate codes for the protocol validation, for the network simulation, and for the system implementation, the unified code can be used for the network simulation and the implementation of software and hardware. Our MAC architecture is partitioned into two parts, Upper-layer MAC and Lower-layer MAC, in order to achieve the high efficiency for the new features of IEEE 802.11n standard. They are implemented in software and hardware respectively. The implemented MAC is tested on ARM based FPGA board.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.376-386
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• 2020

The aim of this study was to develop a new efficient strategy that uses the Vector form Intrinsic Finite-element (VFIFE) method to conduct the static and dynamic analyses of marine pipes. Nonlinear problems, such as large displacement, small strain, and contact and collision, can be analyzed using a unified calculation process in the VFIFE method according to the fundamental theories of point value description, path element, and reverse motion. This method enables analysis without the need to integrate the stiffness matrix of the structure, because only motion equations of particles established according to Newton's second law are required. These characteristics of the VFIFE facilitate the modeling and computation efficiencies in analyzing the nonlinear dynamic problem of flexible pipe with large deflections. In this study, a three-dimensional (3-D) dynamical model based on 3-D beam element was established according to the VFIFE method. The deep-sea flexible pipe was described by a set of spatial mass particles linked by 3-D beam element. The motion and configuration of the pipe are determined by these spatial particles. Based on this model, a simulation procedure to predict the 3-D dynamical behavior of flexible pipe was developed and verified. It was found that the spatial configuration and static internal force of the mining pipe can be obtained by calculating the stationary state of pipe motion. Using this simulation procedure, an analysis was conducted on the static and dynamic behaviors of the flexible mining pipe based on a 1000-m sea trial system. The results of the analysis proved that the VFIFE method can be efficiently applied to the static and dynamic analyses of marine pipes.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• Journal of the Korea Society of Computer and Information
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• v.27 no.3
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• pp.63-69
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• 2022

In this paper, we propose a new GPU-based framework for quickly calculating adaptive and continuous SDF(Signed distance fields), and examine cases related to rendering/collision processing using them. The quadtree constructed from the triangle mesh is transferred to the GPU memory, and the Euclidean distance to the triangle is processed in parallel for each thread by using it to find the shortest continuous distance without discontinuity in the adaptive grid space. In this process, it is shown through experiments that the cut-off view of the adaptive distance field, the distance value inquiry at a specific location, real-time raytracing, and collision handling can be performed quickly and efficiently. Using the proposed method, the adaptive sign distance field can be calculated quickly in about 1 second even on a high polygon mesh, so it is a method that can be fully utilized not only for rigid bodies but also for deformable bodies. It shows the stability of the algorithm through various experimental results whether it can accurately sample and represent distance values in various models.