• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.29-32
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• 2002

This paper describes a novel structure of NMOSFET with elevated SiGe source/drain region and ultra-shallow source/drain extension(SDE)region. A new ultra-shallow junction formation technology. Which is based on damage-free process for rcplacing of low energy ion implantation, is realized using ultra-high vacuum chemical vapor deposition(UHVCVD) and excimer laser annealing(ELA).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.349-352
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• 2001

본 논문은 기가 SRAM급 이상의 초고집적을- 위한 0.1$\mu\textrm{m}$의 설계치수를 갖는 MOSFET의 게이트 영역에서 활성 부분의 면저항을 감소시키기 위해 n영역으로 비소를 이온 주입하였다. 어닐링은 급속 열처리 공정 방법과 엑시머 레이져 어닐링 방법을 이용하였으며, 극히 얕은 접합의 형성이 가능하였다. 얕은 접합 형성 깊이는 10~20nm이며, 비소의 주입량은 2$\times$$10^{14}$ $\textrm{cm}^2$이고, 레이져는 엑시머이며 소스는 KrF로 파장은 248mm로 어닐링 하였다. 극히 얕은 P/N$^{+}$ 접합 깊이가 15nm이며, 이때 1k$\Omega$/$\square$의 낮은 면저항 특성을 갖는 결과가 나타났다.

• 전자공학회논문지D
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• 제35D권5호
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• pp.87-92
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• 1998

Ultr shallow p$^{+}$-n junction with Co/Ti bilayer silicidde contact was formed by ion implantation of BF$_{2}$ [energy : (30, 50)keV, dose:($5{\times}10^{14}$, $5{\times}10^{15}$/$\textrm{cm}^2$] onto the n-well Si(100) region and by RTA-silicidation and post annealing of the evaporated Co(120.angs., 170.angs.)/Ti(40~50.angs.) double layer. The sheet resistance of the silicided p$^{+}$ region of the p$^{+}$-n junction formed by BF2 implantation with energy of 30keV and dose of $5{\times}10^{15}$/$\textrm{cm}^2$ and Co/Ti thickness of $120{\AA}$/(40~$50{\AA}$) was about $8{\Omega}$/${\box}$. The junction depth including silicide thickness of about $500{\AA}$ was 0.14${\mu}$. The fabricated p$^{+}$ -n ultra shallow junction depth including silicide thickness of about $500{\AA}$ was 0.14${\mu}$. The fabricated p$^{+}$-n ultra shallow junction with Co/Ti bilayer silicide contact did not show any agglomeration or variation of sheet resistance value after post annealing at $850^{\circ}C$ for 30 minutes. The boron concentration at the epitaxial CoSi$_{2}$/Si interface of the fabricated junction was about 6*10$6{\times}10^{19}$ / $\textrm{cm}^2$./TEX>.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• 한국재료학회지
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• 제13권6호
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1997년도 제12회 학술발표회 논문개요집
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• pp.81-81
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• 1997

• 한국재료학회지
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• 제8권5호
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• pp.470-473
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• 1998

Co/Ti 이중막을 급속열처리하여 형성한 $CoSi_{2}$에 $As^+$을 이온주입한 후, 500~$1000^{\circ}C$에서 drive-in 열처리하여 매우얇은 $n_{+}$ p접합의 다이오드를 제작하고 I-V 특성을 측정하였다. $500^{\circ}C$에서 280초 drive-in 열처리하였을 때, 50nm정도의 매우 얇은접합이 형성되었고, 누설전류가 매우 낮아 가장 우수한 다이오드 특성을 나타내었다. 특히, Co 단일막을 사용한 다이오드에 비해 누설전류는 2order 이상 낮았으며, 이는 $CoSi_{2}$Si의 계면이 균일하였기 때문이다.

• 한국진공학회지
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• 제6권4호
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• pp.326-336
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• 1997

트랜지스터의 소오스/드레인 접합 특성에 가장 큰 영향을 미치는 인자는 이온 주입 시 발생한 실리콘 내에 발생한 결합이라는 사실에 착안하여, 기존 소오스/드레인 접합 형성 공정과 다른 새로운 방식을 도입하여 이온 주입에 의해 생긴 결함의 제어를 통해 고품질 초 저접합 $p^+$-n접합을 형성하였다. 기존의 $p^+$소오스/드레인 접합 형성 공정은 $^{49}BF_2^+$ 이온 주입 후 층간 절연막들인 TEOS(Tetra-Ethyl-Ortho-Silicate)막과 BPSG(Boro-Phospho-Silicate-Glass)막을 증착 후 BPSG막 평탄화를 위한 furnace annealing 공정으로 진행된다. 본 연구에서는 이러한 기존 공정과는 달리 층간 절연막 증착 전 저온 RTA첨가 방법, $^{49}BF_2^+$와 $^{11}B^+$ 을 혼합하여 이온 주입하는 방법, 그리고 이온 주입 후 잔류 산화막을 제거하고 MTO(Medium temperature CVD oxide)를 증착하는 방법을 제시하 였으며, 각각의 방법은 모두 이온 주입에 의한 실리콘 내 결합 농도를 줄여 기존의 방법보 다 더 우수한 양질의 초 저접합을 형성할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.585-588
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• 1998

We investigated the ultra-low energy B, P, and As ion implantation using ungraded MDRANGE code to form nanometer junction depths. Even at the ultra-low energies that were simulated in paper, it was found that channeling cases must be carefully considered. In the cases of B, channeling occurred above 500 eV, in the cases of P, channeling occurred above 1 keV, and in the cases of As, channeling occurred above 2 keV. Comparing 2D dopant profiles of 1 keV B, 2 keV P, and 5 keV As with tilts, we demonstrated that most channeling cases occurred not lateral directions but depth directions. Through thus results, even below 5 keV energy ion implant considered here, it is estimated that channeling effects are important in the formation of nanometer junction depths.