• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.71-79
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• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

• Restorative Dentistry and Endodontics
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• v.27 no.5
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• pp.488-492
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• 2002

The purpose of this study was to evaluate the effectiveness of plasma arc curing (PAC) unit for composite and compomer curing. To compare its effectiveness with conventional quartz tungsten halogen (QTH) light curing unit, the polymerization shrinkage rates and amounts of three composites (Z100, Z250, Synergy Duo Shade) and one compomer, that had been light cured by PAC unit or QTH unit, was compared using a custome made linometer. The measurement of polymerization shrinkage was peformed after polymerization with either QTH unit or PAC unit. In case of curing with the PAC unit, the composite was light cured with Apollo 95E for 6s, the power density of which was recorded as 1350 mW/$\textrm{cm}^2$ by Coltolux Light Meter. For light curing with QTH unit, the composite was light cured for 30s with the XL2500, the power density of which was recorded as 800 mW/$\textrm{cm}^2$ by Coltolux Light Meter. The amount of linear polymerization shrinkage was recorded in the computer every 0.5s for 60s. Ten measurements were made for each material. The amount of linear polymerization shrinkage for each material in 10s and 60s which were cured with PAC or QTH unit were compared with t test. The amount of polymerization shrinkage in the tested materials were compared with 1way ANOVA with Duncan's multiple range test. As for the amounts of polymerization shrinkage in 60s, there was no difference between PAC unit and QTH unit in Z250 and Synergy Duo Shade. In Z100 and Dyract AP, it was lower when it was cured with PAC unit than when it was cured with QTH unit (p<0.05). As for the amounts of polymerization shrinkage in 10s, there was no difference between PAC unit and QTH unit in Z100 and Dyract AP. The amounts of polymerization shrinkage was significantly higher when it was cured with PAC unit in Z250 and Synergy Duo Shade (p<0.05). The amounts of polymerization shrinkage in the tested materials when they were cured with QTH unit were Z250 (6.6um) < Z100 (9.3um), Dyract AP (9.7um) < Synergy Duo Shade (11.2um) (p<0.05). The amount of polymerization shrinkage when the materials were cured with PAC unit were Dyract AP (5.6um) < Z100 (8.1um), Z250(7.0um) < Synergy Duo Shade (11.2um) (p<0.05).

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.399-401
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• 2008

• Journal of the Korean Statistical Society
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• v.17 no.2
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• pp.134-145
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• 1988

The basic conditions for a parallel-flats fraction to be a search design of Resolution III.2 have been developed in Um (1980, 1981, 1983, 1984). In this paper, a series of resolution III.2 search designs for $3^n, n=4, 5, 6$, are presented.

• 한국도로학회:학술대회논문집
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• 2002.10a
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• pp.187-194
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• 2002

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.316-316
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• 2004

• Proceedings of the Materials Research Society of Korea Conference
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• 2005.05a
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• pp.109-109
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• 2005

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Resources Recycling
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• v.23 no.5
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• pp.55-61
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• 2014

Froth flotation was performed to study the effect of phosphate addition in the experiment to remove As from tailing of Sang-dong Mine. The experiment without Trisodium phosphate (T.S.P) showed that the removal rate of As was 88.7% and weight-ratio of floating material was 2.52%. By contrast, the experiment with T.S.P showed that the removal rate of As was 92.74% and weight-ratio of floating material was 2.26%. In flotation without T.S.P, the average particle size of float material was 19.34 um and the amount less than 10um was 40.2%. On the other hand, in flotation with T.S.P the average particle size of float material was 176.8 um and the amount less than 10um was 6.5%. The result of X.R.F analysis presented that contents of $SiO_2$ was 42.74% in float material of the experiment without T.S.P. In contrast, contents of $SiO_2$ was 29.56% in float material of the experiment with T.S.P.