• Transactions on Electrical and Electronic Materials
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• 제2권2호
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• pp.16-20
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• 2001

Optoelectronic characteristics of the superlattice diode as a function of deposition temperature and annealing conditions have been studied. The multilayer nanocrystalline silicon/adsorbed oxygen (nc/Si/O) superlattice formed by molecular beam epitaxy (MBE) system. Experimental results showed that deposition temperature of 550$^{\circ}C$, followed by hydrogen annealing leads to best results, in terms of optical photoluminescence (PL) and electrical current-voltage (I-V) characteristics. Consequently, the experimental results of multilayer Si/O superlattic device showed the stable photoluminescence and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic devices, and can be readily integrated with conventional silicon ULSI processing.

• 한국표면공학회지
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• 제29권6호
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• pp.803-808
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• 1996

Material and electrical characteristies of copper thin films prepared by metal organic chemical vapor deposition (MOCVD) have been investigated for interconnection applications in ultra large scale integration circuits (ULSI). The copper films have been deposited a TiN substrates using a metal organic precursor, hexafluoro acetylacetonate trimethyvinylsilane copper, VTMS(hfac)Cu (I). Deposition rate, grain size, surface morphology, and electrical resistvity of the copper films have been measuredfrom samples prepared at various experimental conditions, which include substrate temperature, chamber pressure, and carrier gas flow rate. Results of the experiment showed that the electrical property of the copper films is closely related to the crystallinity of the films. Lowest electrical resistivity, $2.4{\mu}{\Omega}.cm$ was obtained at the substrate temperature of $180^{\circ}C$, but the resistivity slightly increased with increasing substrate temperature due to the carbon content along the copper grain boundaries.

• Korea-Australia Rheology Journal
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• 제14권2호
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• pp.71-76
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• 2002

Metal thin films, which are indispensable constituents of ULSI (Ultra Large Scale Integration) circuits, have been fabricated by physical or chemical methods. However, these methods have a drawback of using expensive high vacuum instruments. In this work, the fabrication of tungsten metal film by spin coating was investigated. First of all, inorganic peroxopolytungstic acid (W-IPA) powder, which is soluble in water, was prepared by dissolving metal tungsten in hydrogen peroxide and by evaporating residual solvent. Then, the solution of W-IPA was mixed with organic solvent, which was spin-coated on wafers. And then, tungsten metal films, were obtained after reduction procedure. By selecting an appropriate organic solvent and irradiating UV, the sheet resistance of the tungsten metal film could be remarkably reduced.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.172-176
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• 1996

The rapid structural change of ULSI chip includes minimum features, multilevel interconnection and large diameter wafers. Demands for the advanced chip structure necessitates the development of enhanced deposition, etching and planarization techniques. Planarization refers to a process that make rugged surfaces flat and uniform. One of the emerging technologies for planarization is chemical mechanical polishing(CMP). Chemical and mechanical removal actions occur during CMP, and both appear to be closely interrelated. The purpose of this study is the optimal application of the slurry to the various types of device materials during CMP. We investigates the effect of slurry on CMP characteristics for thermal oxide and sputtered Al blanket wafers. Results from the polishing rate and the uniformity of residual film include mechanical and chemical reactions between several set of slurry and work material.

• Journal of Korean Vacuum Science & Technology
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• 제3권1호
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• pp.1-9
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• 1999

This paper presents a newly enhanced damage model in Monte Carlo (MC) simulation for the accurate prediction of 3-Dimensional (3D) as-implanted impurity and point defect profiles induced by ion implantation in (100) crystal silicon. An empirical electronic energy loss model for B, BF2, As, P and Si self implant over the wide energy range has been proposed for the ULSI device technology and development. Our model shows very good agreement with the SIMS data over the wide energy range. In the damage accumulation, we considered the self-annealing effects by introducing our proposed non-linear recomvination probability function of each point defect for the computational efficiency. For the damage profiles, we compared the published RBS/channeling data with our results of phosphorus implants. Our damage model shows very reasonable agreement with the experiments for phosphorus implants.

• 한국표면공학회지
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• 제32권6호
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• pp.703-708
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• 1999

Silicides have been used extensively in ULSI logic device fabrication as contact materials for the active areas as well as the poly- Si gates. NiSi is a promising candidate for submicron device application due to less volume expansion, low formation temperature, little silicon consumption, and large stable processing temperature window. In this report, the microstructure of nickel silicides fabricated with a thermal evaporator has been investigated. We observed systematic transformation of Ni silicides of $Ni_2$Si, NiSi, $NiSi_2$, as annealing temperature increases. All the silicides have been identified by a X-ray diffractometer (XRD). The cross-sectional microstructure of silicides was examined by a transmission electron microscope (TEM) equipped with a energy dispersive spectrometer(EDS). The surface roughness of silicides was measured by scanning probe microscope(SPM). Although we observed thin oxide layer existed at the $Ni/NiSi_{x}$ interface, we fabricated successfully $550\AA$-thick planar Ni-monosilicide at the temperature range of$ 400~700^{\circ}C$.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.441-446
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• 2003

The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.23-26
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• 2002

In this paper, We have studied the CMP (chemical mechanical polishing) characteristics of diluted slurry by adding of raw alumina abrasive and annealed alumina abrasive. As a experimental results, we obtained the comparable slurry characteristics compared with original silica slurry in the view point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.1267-1268
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• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, we studied the mixed abrasive slurry (MAS). In order to save the costs of slurry, the original silica slurry was diluted by do-ionized water (DIW). And then, $ZrO_2,CeO_2$, and $MnO_2$ abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry. We have also investigate the possibility of mixed abrasive slurry for the oxide CMP application.

• Transactions on Electrical and Electronic Materials
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• 제6권3호
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• pp.87-90
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• 2005

$SiO_2$ via-hole etching with a high aspect ratio is a key process in fabricating ULSI devices; however, accumulated charge during plasma etching can cause etching stop, micro-loading effects, and charge build-up damage. To alleviate this concern, charge-up damage sensor was fabricated for the ultimate goal of real-time monitoring of accumulated charge. As an effort to reach the ultimate goal, fabricated sensor was used for electrical potential measurements of via holes between two poly-Si electrodes and roughly characterized under various plasma conditions using statistical design of experiment (DOE). The successful identification of potential difference under various plasma conditions not only supports the evidence of potential charge-up damage, but also leads the direction of future study.