• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1559-1562
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• 1999

We formed $SiO_2:F$ films by low-temperature process called Liquid Phase Deposition(LPD) and investigated its electrical and physical properties. Because of the use of room-temperature and no special vacuum apparatus for forming $SiO_2:F$ films, this technique can have some advantages related with the application to dielectric interlayer for multilevel structure in ULSI devices. The growth rate 100nm/hr was obtained at the growth solution of 2.5mol/l. The P-etch rate showed a similar or better tendency compared with $SiO_2$ films formed by CVD, Sputter, E-beam evaporator etc.. The fourier transform infrared (FTIR) spectra revealed that the contained fluorine atoms exist uniform throughout the formed $SiO_2$ films. The Scanning Electron Microscope images showed that LPD-$SiO_2$ films could be stably grown on silicon substrates and the good step-coverage could also be obtained, which indicates that the LPD-$SiO_2$ films have some possibility of the application to planarization and interlayer dielectric films which are vitally necessary to achieve the multilevel interconnection in ULSI. The I-V characteristics has some distinct differences according to the concentration of growth solution.

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.321-327
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• 2001

Ti-Si-N films obtained by using RF reactive sputtering of targets with various Ti/Si ratios in a $N_2(Ar+N_2)$ gas mixture have been investigated in terms of films resistivity and diffusion barrier performance. The chemical bonding state of Si in the Ti-Si-N film which contained a higher Si content was in the form of amorphous $Si_3N_4$, producing increased film resistivity with increased $N_2$flow rate. Lowering the Si content in the deposited Ti-Si-N film favored the formation of crystalline TiN even at low $N_2$flow rates, and leads to low film resistivity. In addition increasing the N content led to Ti-Si-N films having a higher density and compressive stress, suggesting that the N content in the films appear to be one of the most important factors affecting the diffusion barrier characteristics. Consequently, we proposed the optimum composition in the range of 29~49 at.% of Ti, 6~20 at.% of Si, and 45~55 at.% of N for the Ti-Si-N films having both low resistivity and excellent diffusion barrier performance.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.283-287
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• 2002

We have studied Zr(Si)N film as a diffusion barrier between Cu metal and Si substrate for application of interconnection metal in ULSI circuits. Zr(Si)N film was deposited with reactive DC magnetron sputtering system using $Ar/N_2$mixed gas. The value of the resistivity was the lowest for the ZrN film using 29 : 1 of Ar : $N_2$reactant gas ratio at room temperature and decreased with increasing of Si substrate temperature. As the value of ZrN film resistivity was decreased, the direction of crystal growth was toward to (002) plane. The barrier property of ZrN film added with Si was improved. But Si was added too much in ZrN film, the barrier property was degraded. The adhesive property was improved with increasing of Si in ZrN. For the analysis of the film, XRD, Optical microscopy, Scretch tester, so on were used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1491-1496
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• 2005

We fabricated the $Pb_{0.72}La_{0.28}TiO_3$ (PLT(28)) thin film successfully by using the sol-gel method and characterized it to evaluate its potential for being utilized as the capacitor dielectrics of ULSI DRAMs. In our sol-gel process, the acetates were used as the starting materials. Through the TGA-DTA analysis, we established the excellent fabrication conditions of the sol-gel method for the PLT(28) thin film. We obtained the dense and crack-free PLT(28) thin film of $100\%$ perovskite phase by drying at $350^{\circ}C$ after each coating and final annealing at $650^{\circ}C$. Electrical properties of PLT(28) thin film were measured through formation on the $Pt/Ti/SiO_2/Si$ substrate and its dielectric constant and leakage current density were measured as 936 and $1.1{\mu}A/cm^2$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.53-58
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• 2005

We researched damage formation and failure mechanism under DC(direct current) and AC(alternative current) in order to estimate reliability of Cu interconnects in ULSI. Higher current density and temperature induces more short TTF(time to failure) during interconnects carry DC. Measurement reveals that Cu electromigration has activation energy of 0.96eV and current density exponent value of 4. Thermal fatigue is occurred under DC, and higher frequency and ${\Delta}$T value gives more severe damage during interconnects carry AC Through failure morphology analysis with respect to texture, we observed that damages had grown widely and facetted grains had appeared in (100)grain but damages in (111) had grown thickness direction of line and had induced a failure rapidly.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.942-945
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• 1999

In this work, we proposed Proper etching algorithm for ultra-large scale integrated circuit device and simulated etching process using the proposed algorithm in the case of ICP (inductive coupled plasma) 〔1〕source. Until now, many algorithms for etching process simulation have been proposed such as Cell remove algorithm, String algorithm and Ray algorithm. These algorithms have several drawbacks due to analytic function; these algorithms are not appropriate for sub 0.1 ${\mu}{\textrm}{m}$ device technologies which should deal with each ion. These algorithms could not present exactly straggle and interaction between Projectile ions and could not consider reflection effects due to interactions among next projectile ions, reflected ions and sputtering ions, simultaneously In order to apply ULSI process simulation, algorithm considering above mentioned interactions at the same time is needed. Proposed algorithm calculates interactions both in plasma source region and in target material region, and uses BCA (binary collision approximation4〕method when ion impact on target material surface. Proposed algorithm considers the interaction between source ions in sheath region (from Quartz region to substrate region). After the collision between target and ion, reflected ion collides next projectile ion or sputtered atoms. In ICP etching, because the main mechanism is sputtering, both SiO$_2$ and Si can be etched. Therefore, to obtain etching profiles, mask thickness and mask composition must be considered. Since we consider both SiO$_2$ etching and Si etching, it is possible to predict the thickness of SiO$_2$ for etching of ULSI.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.95-99
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• 2008

Cu has been used for metallic interconnects in ULSI applications because of its lower resistivity according to the scaling down of semiconductor devices. The resistivity of Cu lines will affect the RC delay and will limit signal propagation in integrated circuits. We investigated the electrolyte effects of the electroplating solution in the resistivity value of Cu films grown by electroplating deposition (EPD). The resistivity was measured with a four-point probe and the material properties were investigated with XRD (X-ray Diffraction), AFM (Atomic Force Microscope), FE-SEM (Field Emission Scanning Electron Microscope) and XPS (X-ray Photoelectron Spectroscopy). From these experimental results, we found that the electrolyte condition plays an Important role in formation of Cu film with lower resistivity by EPD.

• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.136-143
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• 2003

In this paper, high purity RF sputter-type ion source for non-mass separated ion beam deposition was evaluated. The fundamental characteristics of the ion source which is composed of an RF Cu coil and a high purity Cu target (99.9999 %) was studied, and the practical application of Cu thin films for ULSI metallization was discussed. The relationship between the DC target current and the DC target voltage at various RF power and Ar gas pressures was measured, and then preparation conditions for Cu thin films was described. As a result, it was found that the deposition conditions of the target voltage, the target current and the Ar pressure were optimized at -300 V, 240 W and 9 Pa, respectively. The resistivity of Cu films deposited at a bias voltage of -50 V showed a minimum value of 1.8 $\pm$ 0.1 $mu\Omega$cm, which is close to that of Cu bulk (1.67 $mu\Omega$cm).

• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.42-43
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• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.