• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1180-1182
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• 1993

In this paper, studing for the formative characterizations, bonding structures and hydrogen atom content in layer that oxynitride films deposited by Plasma CVD was investigated adaptive possibility for intemediate layer or final passivation layer of ULSI semiconductor devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.185-186
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• 2005

Intrinsic gettering is usually used to improve wafer quality which is an important factor for reliable ULSI devices. The two-step annealing method was adopted in order to investigate interactions between oxygens and secondary defects during oxygen precipitation process in lightly and heavily boron doped silicon wafers with high energy $^{11}B^+$ ion implantation. Secondary defects were inspected nearby the projected range by high resolution transmission electron microscopy. Oxygen pileup was measured in the vicinity of the projected range by secondary ion mass spectrometry for heavily boron doped silicon wafers.

• Journal of the Korean Vacuum Society
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• v.9 no.1
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• pp.69-75
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• 2000

We have investigated the feasibility of spin on glass (SOG) film from polysilazane-type resin as a premetal dielectric (PMD) layer of the next-generation ultra-large scale integrated (ULSI) devices. A commercial polysilazane resin and a polysilazane-type resin with oxidizing agent were spin-coated and cured to form SOG films. In order to study the effect of oxidizing agent and annealing, the SOG films were characterized as cured and after annealing at $400^{\circ}C$ to $900^{\circ}C$. the density and the resistance against wet chemical of the SOG films were improved by the addition of oxidizing agent, because oxidizing agent enhanced the conversion from polysilazane polymer to $SiO_2$. The hole profile issue associated with insufficient curing of polysilazane in narrow gaps was also resolved by oxidizing agent, while the gapfill capability of SOG was not deteriorated by oxidizing agent.

• Journal of the Korean Vacuum Society
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• v.4 no.3
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• pp.270-274
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• 1995

The growth structure of Fe on CU(001) was studied by scanning tunneling microscope. An analysis of size distribution of Fe islands on Cu(001) surface was made to determine whether Fe atoms mix with substrate Cu. The size distribution deviates from the standard scaling behavior, indicating that atomic density of Fe decreases with coverage up to 1 ML. The growth can be characterized by layer-by-layer scheme from 1 ML to 5 ML. This result agrees well with previously studied, Auger spectroscopy and RHEED result.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.5
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• pp.32-37
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• 2004

Polishing processes are widely used in the glass, optical, die and semiconductor industries. Chemical Mechanical Polishing (CMP) especially is becoming one of the most important ULSI processes for the 0.25m generation and beyond. CMP is conventionally carried out using abrasive slurry and a polishing pad. But the surface of the pad has irregular pores, so there is non-uniformity of slurry flow and of contact area between wafer and the pad, and glazing occurs on the surface of the pad. This paper introduces the basic concept and fabrication technique of the next generation CMP pad using micro-molding method to obtain uniform protrusions and pores on the pad surface.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.11
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• pp.46-56
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• 1996

Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.771-780
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• 2001

It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.18-24
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• 2000

(Ba,Sr)$TiO_3$ thin films have attracted great interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2/Ar$ plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage=600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2 the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is $480{\AA}/min$ at 10 % $BCl_3$ to $Cl_2/Ar$. The change of Cl, B radical density measured by optical emission spectroscopy(OES) as a function of $BCl_3$ percentage in $Cl_2/Ar$. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2/Ar$. To study on the surface reaction of (Ba, Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion bombardment etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and $TiCl_4$ is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about 65~70$^{\circ}$.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.518-522
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• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• Korean Journal of Materials Research
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• v.14 no.8
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• pp.573-578
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• 2004

Newly developed silicide materials for ULSI should have the appropriate electrical property of low resistant as well as process compatibility in conventional CMOS process. We prepared $NiCoSi_x$ silicides from 15 nm-Co/15 nm-Ni/Si structure and performed contact dry etch process to confirm the dry etch stability and compatibility of $NiCoSi_x$ layers. We dry etched the photoresist/SiO/silicide/silicon patterns with $CF_4\;and\;CHF_3$ gases with varying powers from 100 to 200 W, and pressures from 45 to 65 mTorr, respectively. Polysilicon and silicon active layers without silicide were etched $0\sim316{\AA}$ during over etch time of 3min, while silicon layers with proposed $NiCoSi_x$ silicide were not etched and showed stable surfaces. Our result implies that new $NiCoSi_x$ silicides may replace the conventional silicides due to contact etch process compatibility.