• Title/Summary/Keyword: ULSI

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A Design of Beam Steeringn-phase OPTO-ULSI Processor for IIPS (IIPS를위한 광선 제어용n-위상 OPTO-ULSI 프로세서의 디자인)

  • Lee, Chang-Ki;Im, Hyung-Kyu
    • Journal of the Korea Computer Industry Society
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    • v.5 no.2
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    • pp.261-268
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    • 2004
  • This study to design an optimum phase implementing a 256 phase Opto-ULSI processor for multi-function capable optical networks. The design of an 8 phase processor is already in construction and will provide the Initial base for experimentation and characterisation. The challenge is to be able to compensate for the non-linearity of the liquid crystal, find an optimum phase, and implement a larger scale Opto-ULSI processor. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the non-linearity of liquid crystal.

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Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS (IIPS를 위한 빔 조향 n위상 광 ULSI 프로세서 디자인)

  • Lee, Chang-Ki;Lim, Hyung-Kyu
    • The Journal of the Korea institute of electronic communication sciences
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    • v.3 no.3
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    • pp.158-164
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    • 2008
  • This project investigates an optimum phase design implementing a 256 phase Opto-ULSI processor for multi-function capable optical networks. The design of an 8 phase processor is already in construction and will provide the initial base for experimentation and characterization. The challenge is to be able to compensate for the non-linearity of the liquid crystal, find an optimum phase, and implement a larger scale Opto-ULSI processor. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering(BS) Opto-ULSI processor(OUP) for integrated intelligent photonic system(IIPS), while investigating the optimal phase characteristics and developing compensation for the non-linearity of liquid crystal.

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Preparatio and properties of the paraelectric PLT thin film for the cpapcitor dielectrics of ULSI DRAM (ULSI DRAM의 캐패시터 절연막을 위한 Paraelectric PLT 박막의 제작과 특성)

  • 강성준;윤영섭
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.8
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    • pp.78-85
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    • 1995
  • We fabricated the Pb$_{1-0.28{\alpha}}La_{0.28}TiO_{3}$ (PLT(28)) thin film successfully by using the sol-gel method and characterized it to evaluate its potential for being utilized as the capacitor dielectrics of ULSI DRAMs. In our sol-gel process, the acetates were used as the starting materials. Through the TGA-DTA analysis, we established the excellent fabrication conditions of the sol-gel method for the PLT(28) thin film. We obtained the dense and crack-free PLT(28) thin film of 100% perovskite phase by drying at 350$^{\circ}C$ after each coating and final annealing at 650$^{\circ}C$. Its electrical properties were measured from the planar capacitors fabricated on the Pt/Ti/SiO$_{2}$/Si substrate. By the P-E hysteresis measurement, its paraelectric phase was identified and its dielectric constant and leakage current density were measured as 936 and 1.1${\mu}A/cm^{2}$, respectively. Those electrical values indicate that the PLT(28) thin film is the most successful candidate for the capacitor dielectrics of ULSI DRAMs at the present.

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ECR-PECVD PZT Thin Films for the Charge Storage Cpacitor of ULSI DRAMs (ECR-PECVD법을 사용한 ULSI DRAM 용 PZT 박막 제조)

  • 김재환;신중식;김성태;노광수;위당문;이원종
    • Journal of the Korean Vacuum Society
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    • v.4 no.S1
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    • pp.145-150
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    • 1995
  • PZT thin films were fabricated on Pt/Ti/SiO2/Si substrates at $500^{\circ}C$ by ECR-PECVD for the application to the charge storage capacitor of ULSI DRAMs. Perovskite single phase PZT films were obtained by controling the film compositional ratio Pb/(Zr+Ti) close to 1. The anion concentrations in the PZT films were successfully controlled by adjusting the flow rates of each MO sources. Capacitance of a typical 94 nm thick PZT film prepared at $500^{\circ}C$ in this work was about 5.3 uF/$\textrm{cm}^2$, which corresponds to the equivalent SiO2 thickness of 0.65nm.

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