• Journal of Power Electronics
• /
• 제17권5호
• /
• pp.1256-1267
• /
• 2017

A fault tolerant structure and its corresponding control strategy for electromagnetic stirring power supplies are proposed in this paper. The topology structure of the electromagnetic stirring power supply contains two-stages. The fore-stage is the PWM rectifier. The back-stage is the fault tolerant inverter, which is a two-phase three-bridge orthogonal inverter circuit while operating normally. When the power switch devices in the inverter are faulty, the structure of the inverter is reconfigured. The two-phase half bridge inverter circuit is constructed with the remaining power switch devices and DC-link capacitors to keep the system operating after cutting the faulty power switch devices from the system. The corresponding control strategy is proposed to let the system work under both normal and fault conditions. The reliability of the system is improved and the requirement of the electromagnetic stirring process is met. Finally, simulation and experimental results verify the feasibility of the proposed fault tolerant structure and corresponding control strategy.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1995년도 하계학술대회 논문집 A
• /
• pp.168-170
• /
• 1995

This paper proposes the circuit of the simple synthetic testing facility using LC resonance circuit. The analyzed results of the circuit which can be useful for the design stage of the testing facility are also shown. EMTP has been used to analyze the circuit. Two cases of short-circuit test results obtained from the simple synthetic testing facility in KERI are shown with the waveforms of current and voltage. The results also indicate that the simple synthetic testing facility using LC resonance circuit can be easily designed and used very usefully for the research and development for the switchgears.

• 전력전자학회논문지
• /
• 제26권2호
• /
• pp.82-89
• /
• 2021

This study proposes a DAB two-stage series structure with insulated bidirectional DC-DC converter for two-way power transfer between the renewable energy of high voltages (1 kV and above). The proposed circuit transforms the existing DAB converter into a two-stage series structure to reduce the pressure in the switch. The problem of power imbalance occurring in the design of the DAB converter second-stage series is improved by applying the cell balancing method circuit and the common mode coupled inductor using an external flying capacitor instead of reflecting the existing improvement measures, voltage balance control, and inductor current control. In addition, a no-load supercharging sequence is proposed in high voltages and high-speed switching by using the fixed duty output method. This study presents the analysis results through the structure of the proposed circuit, the principle of improving the power imbalance problem, and simulations. Prototypes were manufactured to meet the specifications of input/output voltage of 1700 V, maximum load of 65 kW, and switching frequency of 51kHz, and the validity of the topology was verified using the experimental results and efficiency data.

• Journal of Electrical Engineering and Technology
• /
• 제11권3호
• /
• pp.644-652
• /
• 2016

This paper presents an improved single-stage ac-dc LED-drive flyback converter using the transformer-coupled lossless (TCL) snubber. The proposed converter is derived from the integration of a full-bridge diode rectifier and a conventional flyback converter with a simple TCL snubber. The TCL snubber circuit is composed of only two diodes, a capacitor, and a transformer-coupled auxiliary winding. The TCL snubber limits the surge voltage of the switch and regenerates the energy stored in the leakage inductance of the transformer. Also, the switch of the proposed converter is turned on at a minimum voltage using a formed resonant circuit. Thus, the proposed converter achieves high efficiency. The proposed converter utilizes only one general power factor correction (PFC) control IC as its controller and performs both PFC and output power regulation, simultaneously. Therefore, the proposed converter provides a simple structure and an economic implementation and achieves a high power factor without the need for any separate PFC circuit. In this paper, the operational principle of the proposed converter is explained in detail and the design guideline of the proposed converter is briefly shown. Experimental results for a 40-W prototype are shown to validate the performance of the proposed converter.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.226-228
• /
• 2005

This paper presents the single-stage High Power Factor TTFC(Two-Transistor Forward Converter). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contests of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output.

• 전자공학회논문지
• /
• 제51권1호
• /
• pp.52-56
• /
• 2014

본 논문은 고효율 전력증폭기는 무선전력전송을 위한 게이트와 드레인 바이어스 조절 회로를 사용하여 설계하였다. 이 조절 회로는 PAE (Power Added Efficiency)를 개선하기 위해 사용되었다. 게이트와 드레인 바이어스 조절 회로는 directional coupler, power detector, and operational amplifier로 구성되어있다. 구동증폭기를 사용하여 고이득 2단 증폭기는 전력증폭기의 낮은 입력단에 사용되었다. 게이트와 드레인 바이어스 조절회로를 사용하여 제안된 전력증폭기는 낮은 전력에서 높은 효율성을 가질 수 있다. PAE는 80.5%까지 향상되었고 출력전력은 40.17dBm이다.

• Journal of Power Electronics
• /
• 제15권4호
• /
• pp.1131-1138
• /
• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• 전기전자학회논문지
• /
• 제28권1호
• /
• pp.78-89
• /
• 2024

차량용 반도체에서 사용되는 BCD 공정 기반의 PMIC 칩은 아날로그 회로를 트리밍하기 위해 추가 마스크가 필요없는 MTP(Multi-Time Programmable) IP(Intellectual Property)를 요구한다. 본 논문에서는 저면적 MTP IP 설계를 위해 2개의 트랜지스터와 1개의 MOS 커패시터를 갖는 single poly EEPROM 셀인 MTP 셀에서 NCAP(NMOS Capacitor) 대신 PCAP(PMOS Capacitor)을 사용한 MTP 셀을 사용하여 MTP 셀 사이즈를 18.4% 정도 줄였다. 그리고 MTP IP 회로 설계 관점에서 MTP IP 설계의 CG 구동회로와 TG 구동회로에 2-stage voltage shifter 회로를 적용하였고, DC-DC 변환기 회로의 면적을 줄이기 위해 전하 펌핑 방식을 사용하는 VPP(=7.75V), VNN(=-7.75V)와 VNNL(=-2.5V) 전하 펌프 회로에서 각각의 전하 펌프마다 별도로 두고 있는 ring oscillator 회로를 하나만 둔 회로를 제안하였으며, VPPL(=2.5V)은 전하펌프 대신 voltage regulator 회로를 사용하는 방식을 제안하였다. 180nm BCD 공정 기반으로 설계된 4Kb MTP IP 사이즈는 0.493mm²이다.

• 한국정보통신학회논문지
• /
• 제12권2호
• /
• pp.282-289
• /
• 2008

PDP TV의 전력 효율을 향상시키기 위해서는 PDP의 구동과정에서 발생하게 되는 불필요한 전력소모와 AC 입력으로부터 원하는 DC를 얻기 위한 과정 중에 발생하는 전력 소모를 최소화하여야 한다. 일반적인 PDP 구동을 위한 입력 전원단은 2단 구조의 역률 보상형 컨버터를 채용하고 있으며, PDP 구동시 전력소모가 가장 큰 서스테인 드라이버와 리셋 회로의 구동전원을 공급하기 위한 별도의 DC-to-DC 컨버터를 필요로 한다. 그러나 이러한 회로의 구현은 저가의 PDP를 요구하는 시장 상황에 유연하게 대처하는데 많은 어려움을 준다. 따라서 본 논문에서는 최소의 전력 변환단계를 가지도록 서스테인과 리셋 회로의 전원 공급이 가능한 1단방식의 역률보상형 AC-to-DC 컨버터를 제안한다. 제안하는 시스템은 1단방식의 입력전원부 구성을 통해 전력 변환단을 최소화하여 전력 변환 중에 발생하는 손실을 최소화하며, PDP 서스테인/리셋 드라이버의 구동전압을 직접 공급하는 형태로 구성하여 시스템 부피의 감소, 원가 절감을 이룰 수 있다.

• Journal of Power Electronics
• /
• 제6권4호
• /
• pp.330-339
• /
• 2006

This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for ($2{\times}36$ Watt) fluorescent lamps operating at 50 kHz switching frequency and input line voltage (230 V, 50 Hz).