• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.367-368
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• 2016

10kV IGCT has been recently developed and has the potential to push wind turbine systems to higher power and voltage rating. Converters employing IGCTs need snubber and OVP circuit to limit the rate of current's rising and peak over voltage across IGCT during turn on and off state, respectively. The conventional RCD snubber which is used in such power converter dissipates a significant amount of power. In order to reduce the amount of energy lost by conventional RCD snubber, this paper proposes flyback type snubber comprising two coils wound on a magnetic core. The flyback snubber not only meets all of the IGCTs characteristics during on and off-state but also significantly saves the power loss. Modern magnetic model using permeance-capacitance analogy leads to more accurate loss analysis of flyback type di/dt snubber circuit in 3-level NPC type back-to-back VSC. In turns, the comparison between conventional and flyback type snubber yield the effectiveness of proposed snubber in wind turbine systems.

• Journal of Korean Society for Atmospheric Environment
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• v.18 no.6
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• pp.503-514
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• 2002

During the past two decades, primary pollutants in the ambient air have been substantially reduced in Korea by aggressive government efforts such as the switchover to clean fuels and equipment of automobiles with a three-way catalytic converter. However, visibility impairment in Seoul and major metropolitan areas has been a stubborn problem. It is apparent that both directly emitted fine particles mainly from vehicles and secondary fine particles from photochemical reactions could contribute to this visibility impairment. In addition, Korea is located downwind of the prevailing westerlies from China and is influenced by the emissions of air pollutants in China. In order to assess this complicated problem of visibility impairment, the visibility trends for the past 17 years observed at more than 60 stations throughout the country were analyzed. The results showed that visibilities were generally the lowest in the winter morning in comparison with those in the summer afternoon as well as the annual average values. It was believed that primary pollution was principally responsible for visibility impairment in most areas. The visibility in the summer afternoon was lower in clean coastal areas along with a high level of relative humidity due to the inflow of moist air accompanied by sea breeze. Although contributions of secondary particles from photochemical reactions and long-range transport of fine particles to the visibility impairment were probable, their certain evidences were not found.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.6
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• pp.539-546
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• 2014

This paper describes an ultra-precision electronic clinometer, which is based on the capacitive-based fluid type, for detection of small inclination angles. The main parts of the clinometer low-noise electronics are two capacitance measurement circuits for converting the capacitances of the capacitors of the clinometer into voltages, and a differential amplifier for obtaining the difference of the capacitances, which is proportional to the input inclination angle. A 16 bit analog to digital (AD) converter is also embedded into the same circuit board, whose output is sent to a PC via RS-232C, for achieving a small noise level down to tens of ${\mu}v$. A compensation method, which is referred to as the delay time method for shortening the stabilization time of the sensor was also discussed. Experimental results have shown the possibility of achieving a measurement resolution of $0.0001^{\circ}$ as well as the quick measurement with the delay time method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.1
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• pp.8-15
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• 2018

New methodology for probabilistic reliability based grid expansion planning of HVDC in power system including Wind Turbine Generators(WTG) is developed in this paper. This problem is focused on scenario based optimal selection technique to decide best connection bus of new transmission lines of HVDC in view point of adequacy reliability in power system including WTG. This requires two kinds of modeling and simulation for reliability evaluation. One is how is reliability evaluation model and simulation of WTG. Another is to develop a failure model of HVDC. First, reliability evaluation of power system including WTG needs multi-state simulation methodology because of intermittent characteristics of wind speed and nonlinear generation curve of WTG. Reliability methodology of power system including WTG has already been developed with considering multi-state simulation over the years in the world. The multi-state model already developed by authors is used for WTG reliability simulation in this study. Second, the power system including HVDC includes AC/DC converter and DC/AC inverter substation. The substation is composed of a lot of thyristor devices, in which devices have possibility of failure occurrence in potential. Failure model of AC/DC converter and DC/AC inverter substation in order to simulate HVDC reliability is newly proposed in this paper. Furthermore, this problem should be formulated in hierarchical level II(HLII) reliability evaluation because of best bus choice problem for connecting new HVDC and transmission lines consideration. HLII reliability simulation technique is not simple but difficult and complex. CmRel program, which is adequacy reliability evaluation program developed by authors, is extended and developed for this study. Using proposed method, new HVDC connected bus point is able to be decided at best reliability level successfully. Methodology proposed in this paper is applied to small sized model power system.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.