• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.7
• /
• pp.799-803
• /
• 2010

The KDB-tree is a traditional indexing scheme for retrieving multidimensional data. Much research for KDB-tree family frequently addresses the low storage utilization and insufficient retrieval performance as their two bottlenecks. The bottlenecks occur due to a number of unnecessary splits caused by data insertion orders and data skewness. In this paper, we propose a novel index structure, called as $KDB_{CS}^+$-tree, to process skewed data efficiently and improve the retrieval performance. The $KDB_{CS}^+$-tree increases the number of fan-outs by exploiting bit-vectors for representing splitting information and pointer elimination. It also improves the storage utilization by representing entries as a hierarchical structure in each internal node.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.781-792
• /
• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.9
• /
• pp.12-17
• /
• 2016

In the holographic data storage system (HDSS), the data regarding the volume of a storage medium are recorded and read by the page, and the transmission rate and storage capacity can be increased because of two-dimensional, page-oriented data processing; furthermore, the multi-level HDSS can store more than one bit per pixel. For this same reason, however, and unlike conventional data-storage systems, the HDSS is hampered by two-dimensional (2D) intersymbol interference (ISI) and interpage interference (IPI). Progress regarding the published papers on 2D ISI, which is more severe in the multi-level HDSS, continues; however, mitigation of both 2D ISI and IPI in terms of the multi-level HDSS has not yet been studied. In this paper, we therefore propose a 4-level balanced-modulation code that simultaneously mitigates 2D ISI and IPI.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.10
• /
• pp.827-832
• /
• 2013

Holographic data storage system is affected by two dimensional intersymbol interference and inter-page interference. Especially, for multi-level holographic data storage system, since one pixel contains more than 1 bit, the system is more vulnerable to the error. In this paper, we propose a 2/3 modulation code for 4-level holographic data storage system. The proposed modulation code with error correcting capability could be compensated these interferences. Also, in this paper, we proposed a Viterbi decoder for 2/3 modulation code. The proposed Viterbi decoder eliminates unnecessary calculation. As a result, proposed 2/3 modulation code and Viterbi decoder has shown better performance than conventional one.

• The Journal of the Acoustical Society of Korea
• /
• v.17 no.4E
• /
• pp.17-21
• /
• 1998

This paper presents an implementation of a multi-channel speech surveillance system over telephone lines using TMS320C31 DSP chips. The incoming speech into each telephone line are first compressed simultaneously in real-time by the popular vector-sum excited linear predictive (VSELP) speech coding algorithm at the rate of 8 Kbps. The compressed steech bit streams are then multiplexed with those of other users. The multiplexed speech bit streams are transferred to the system storage equipments with some other required information so that a system operator can later monitor the stored speech data whenever it is necessary. The host program runs under Microsoft Windows95 for an efficient man-machine interface and a future upgrade-ability. We have confirmed that the overall 64-channel system operates satisfactorily in realtime. We also have checked approximately up to 2,880 total hours of recording capability of the system on a playback module and two removable backup drives.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.2C
• /
• pp.163-168
• /
• 2009

In this paper, a two-dimensional (2D) modulation code is introduced. The proposed code does not have any isolated pixel that is the most unwanted problem for holographic data storage. The proposed 2D modulation code is simpler than conventional 6/8 code and removes all the isolated 2D ISI patterns. As a result, when the grade of blur is 1.4, the proposed modulation code has better performance overall than conventional 6/8 modulation code. The proposed code has the optimal performance when 4bit quantization is applied.

• 전기의세계
• /
• v.26 no.1
• /
• pp.71-76
• /
• 1977

It has been expected that the 4th generation computers will be characterized for their problem adaptability. There are few techniques of implementing such a characteristic. One of the techniques that one have considered in this paper the user microprogrammable computer architecture. There are two different computer architectures that support user microprogramming. One uses the writeable control storage and another uses the main memory. The concept of utilizing writeable control storage for microprogramming was developed in 1950's and since then the most of the user microprogrammable computers produced belong to such category. The concept of utilizing the main memory for user microprogramming was first introduced by Thomas in 1973. This architecture has a strong advantage in the aspect of the system cost. In this paper, we have developed a user microprogrammable computer. The computer utilizes the main memory for user microprograms. It employs a 32 bit micro-instruction word in the form of the little encoded. The performance of the developed machine will be evaluated in the hard ware cost, programming easiness and the running time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.5
• /
• pp.499-503
• /
• 2016

We study algorithms that can efficiently find cube roots by modifying Cipolla-Lehmer algorithm. In this paper, we present two type algorithms for finding cube roots in finite field, which improves Cipolla-Lehmer algorithm. If the number of multiplications of two type algorithms has a little bit of a difference, then it is more efficient algorithm which have less storage variables.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.10
• /
• pp.833-837
• /
• 2013

Since holographic data storages read and write information on a volume and the information is processed per page, it has the advantage of high recording density and data transfer rate. However, there are two major drawbacks like 2-dimensional intersymbol interference and interpage interference as the density between pixels increases. Furthermore, a bright page that contains many ON pixels influences the reliable detection of the neighboring pages, which causes the less number of pages stored in the storage volume. We propose a sparse-ON pixel two-dimensional modulation code with the code rate 6/8 for increasing the number of pages stored in the volume. The proposed code is compared to conventional 6/8 balanced code, and it shows similar or a little bit better performance than that of the balanced code. Therefore, the proposed code can increase the recording capacity without loss of the performance.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.26 no.1
• /
• pp.5-15
• /
• 2016

Power analysis attacks are techniques to analyze power signals to find out the secrets when cryptographic algorithm is performed. One of the most famous countermeasure against power analysis attacks is masking methods. Masking types are largely classified into two types which are boolean masking and arithmetic masking. For the cryptographic algorithm to be used with boolean and arithmetic masking at the same time, the converting algorithm can switch between boolean and arithmetic masking. In this paper we propose an algorithm for switching from boolean to arithmetic masking using storage size at less cost than ones. The proposed algorithm is configured to convert using the look-up table without the least significant bit(LSB), because of equal the bit of boolean and arithmetic masking. This makes it possible to design a converting algorithm compared to the previous algorithm at a lower cost without sacrificing performance. In addition, by applying the technique at the LEA it showed up to 26 percent performance improvement over existing techniques.