• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.139-149
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• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.

• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.287-294
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• 2005

In this paper, an optical true time-delay (TTD) for two-dimensional (2-D) phased array antennas (PAAs), composed of a multi-wavelength optical source and a fiber optic delay line matrix consisting of $2\times2$ optical switches with optical fiber connected between cross ports, has been proposed. A 2-bit $\times4-bit$ optical TTD for 10-GHz 2-D PAAs has been implemented by cascading a wavelength dependent TTD (WD-TTD) and a wavelength independent TTD (WI-TTD). The unit time delay for WD-TTD and WI-TTD have been chosen as ${\Delta}T=12ps$ and $\Delta\tau=6ps$, respectively. Time delay have been measured at all radiation angles. The maximum delay error for WD-TTD was measured to be 3 ps due to jitter incurred from gain switching. For the case of WI-TTD, error was within ${\pm}\;1\;ps$. The proposed optical TTD for a 2-D PAA has the following advantages: 1) higher gain compared to one-dimensional linear PAAs, 2) stabilization of optical power and wavelength by using a multi-wavelength optical source, and 3) fast beam scan and simple operation due to electronic control of the $2\times2$ optical switches matrix on a column-by-column basis.

• Journal of the Korea Society of Computer and Information
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• v.18 no.12
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• pp.1-9
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• 2013

Even though the multiple pages TLB are effective in improving the performance, a conventional method with OS support cannot utilize multiple page sizes in user application. Thus, we propose a new multiple-TLB structure supporting multiple page sizes for high performance and low power consumption without any operating system support. The proposed TLB is organised as two parts of a S-TLB(Small TLB) with a small page size and a L-TLB(Large TLB) with a large page size. Both are designed as fully associative bank structures. The S-TLB stores small pages are evicted from the L-TLB, and the L-TLB stores large pages including a small page generated by the CPU. Each one bank module of S-TLB and L-TLB can be selectively accessed base on particular one and two bits of the virtual address generated from CPU, respectively. Energy savings are achieved by reducing the number of entries accessed at a time. Also, this paper proposed the simple 1-bit LRU policy to improve the performance. The proposed LRU policy can present recently referenced block by using an additional one bit of each entry on TLBs. This method can simply select a least recently used page from the L-TLB. According to the simulation results, the proposed TLB can reduce Energy * Delay by about 76%, 57%, and 6% compared with a fully associative TLB, a ARM TLB, and a Dual TLB, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.440-447
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• 2007

The switched diversity, although its performance is a little inferior to the selection diversity, is widely used due to its advantage that only one RF circuit is required for its operation without respect to the number of antennas in use. In this paper, we propose an application of the antenna switched diversity to a spread spectrum system with adaptive modulation and derived the optimal antenna switching threshold to maximize the average transmission bit rate. We also compared the performances of the proposed system with those of the two cases using a single antenna and the selection diversity with two antennas in terms of the average number of bits per symbol(BPS), the probability of no transmission, and the average BER. The performance analysis shows that, if the number of paths in a multipath channel environment increases, the performance of the proposed scheme becomes closer to that of the selection diversity based system in terms of the average BPS. Furthermore, the proposed scheme produces as almost high the probability of no transmission as the selection diversity based system for the case of low average SNR, although the former yields a little higher probability of no transmission than the latter fer the case of high average SNR.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.133-142
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• 2005

In this paper, two digital video scrambling methods are proposed as simple means of the digital content protection techniques. One is inter block scrambling using motion vector, the other is intra block scrambling using intra prediction mode. The proposed inter block scrambling method distorts the original sequences by swapping horizontal and vertical components of motion vector. This method can be applied on most common video coding techniques such as MPEG-1, 2, 4, H.264, etc. The proposed intra block scrambling method distorts the original sequences by modifying intra prediction mode that is property of H.254 video coding technique. Both methods do not cause my bit rate increase after scrambling. Moreover, they have low complexity because they need only simple operation like XOR. Especially, the proposed intra block scrambling does not distort inter blocks directly. But inter blocks are distorted by error propagation effect as much as intra blocks. This paper introduces two new digital video scrambling method and verifies its effectiveness through simulation.

• The Journal of Industrial Distribution & Business
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• v.12 no.11
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• pp.33-50
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• 2021

Purpose: In South Korea, two kinds of mandatory insurance, Fierce Liability Insurance and Outdoor Advertising Liability Insurance sells as of February 2021 according to relevant codes. This study analyzed third party liability and personal living liability insurance in terms of various risks not corporation side but personal side arising from normal living and life. Research design, data and methodology: Some cases of drone accident hit man and fierce dog accident were taken into analysis to verify blame ratio and insurance claim money. The former case is that on the way down the elevator, the dog, American pit bull terrier rushed in and bit the lower part of the knee against the visitor. The latter case is that while flying in the sky as usual, the drone suddenly crashed, fell, and hit the head of a young child while walking on the street. Further previous studies such as third party liabilities, liability insurance, mandatory insurance were deeply analyzed. Results: Based on some case studies and previous studies, the author suggested valuable comments in turn realization of insurer as provider, exhaustive creation and operation of mandatory insurance, realization of insured as demanded, and arrangements of laws and systems in special consideration of amendment of companion animal and exhaustive execution of mandatory insurance by the government. Conclusions: This study was about third party liability, personal living liability insurance and expansion of mandatory insurance caused by relevant laws by the government. In this study the author verified what issues were observed from two cases drone accident and fierce dog accident and then suggested some valuable comment as above both systemic plans and practical plans. First of all, the individual should get Comprehensive Property Insurance(CPI) that covers the risks of his/her own property arising from the everyday life. And then the individual should further buy Personal Living Liability Insurance(PLLI) in order to prepare 'accidents that may happen when, where, or how' and overcome the said accidents. Moreover, the individual should take a look every single insurance contract whether he/she has a special terms and conditions of Personal Living Liability Insurance(PLLI) or not.

• Korean Journal of Optics and Photonics
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• v.33 no.3
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• pp.106-112
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• 2022

A two-dimensional optical code division multiple access (OCDMA) encoder/decoder, which is composed of add/drop filters and all-pass filters for delay operation, is proposed. An example design is presented, and its feasibility is illustrated through numerical simulations. The chip area of the proposed OCDMA encoder/decoder could be about one-third that of a previous OCDMA device employing delay waveguides. Its performance is numerically investigated using the transfer-matrix method combined with the fast Fourier transform. The autocorrelation peak level over the maximum cross-correlation level for incorrect wavelength hopping and spectral phase code combinations is greater than 3 at the center of the correctly decoded pulse, which assures a bit error rate lower than 10^-3, corresponding to the forward error-correction limit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.