• 전력전자학회논문지
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• 제20권1호
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• pp.31-37
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• 2015

This paper proposes a 3.3-kW bi-directional EV charger with V2G and V2H functions. The bi-directional EV charger consists of a DC-DC converter and a DC-AC inverter. The proposed EV charger is suitable for wide battery voltage control due to the two-stage configuration of the DC-DC converter. By employing a fixed-frequency series loaded resonant converter as the isolated DC-DC converter, zero-current-switching can be achieved regardless of battery voltage variation, load variation, and power flow. A 3.3-kW prototype of the proposed EV charger has been built and verified with experiments, and indicates a maximum efficiency of 94.39% and rated efficiency of 94.23%.

• 전력전자학회논문지
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• 제19권6호
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• pp.503-510
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• 2014

This study proposes a bi-directional interleaved current-fed resonant converter (CRC) with reduced size of the output filter for a fuel cell electric vehicle. The proposed CRC achieves zero-current switching turn on and off of switches and diodes and makes ripple current of the output capacitor theoretically zero. As a result, the cost and volume of the output capacitor are significantly reduced. The two-stage power conversion technique is also applied for wide input and output voltage range operations. A 2kW prototype of the proposed converter is built and tested to verify the validity of the proposed operation.

• 전력전자학회논문지
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• 제15권5호
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• pp.394-400
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• 2010

본 논문에서는 Buck Converter 동작 원리를 Full -Bridge Inverter에 적용한 전자식 안정기를 제안하였다. 전자식안정기는 EMI 필터, 수동 PFC, Full-Bridge Inverter로 2-stage로 구성되어 있다. PFC는 신뢰성 확보를 위해 수동 PFC를 사용하였다. Full-Bridge Inverter는 High Side와 Low Side 스위치의 구동 주파수를 각각 고주파와 저주파로 구동하여 Buck Converter의 동작을 구현 하였다. 램프를 저주파수 구형파로 구동하여 음향공명현상을 피하게 되었으며, 고주파수 스위칭으로 인덕터의 부피를 줄였다. 제안한 방법은 시뮬레이션과 실험을 통해 증명하였다.

• 전력전자학회논문지
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• 제16권4호
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• pp.382-395
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• 2011

본 논문에서는 다이오드정류기와 커패시터 필터로 구성된 입력전원을 가지고 동작되는 60W이하의 출력파워용량을 갖는 어댑터를 위한 새로운 LLC 공진컨버터에 대한 내용이다. 보조스위치의 동작에 의해 제안된 LLC 공진컨버터는 모든 입력전원 ($110V_{AC}$/ $220V_{AC}$) 및 부하조건에서 높은 효율특성을 가지고 전력을 전달 할 수 있다. 제안된 컨버터에 대한 동작특성에 대해 분석, 서술되어 있으며, 60W 시제품제작 및 실험을 통하여 적용 가능함을 보였다.

• 전기전자학회논문지
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• 제18권4호
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• pp.586-592
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• 2014

본 논문에서는 DT-CMOS(Dynamic Threshold voltage Complementary MOSFET) 스위칭 소자를 사용한 DC-DC Buck 컨버터를 제안하였다. 높은 효율을 얻기 위하여 PWM 제어방식을 사용하였으며, 낮은 온 저항을 갖는 DT-CMOS 스위치 소자를 설계하여 도통 손실을 감소시켰다. 제안한 Buck 컨버터는 밴드갭 기준 전압 회로, 삼각파 발생기, 오차 증폭기, 비교기, 보상 회로, PWM 제어 블록으로 구성되어 있다. 삼각파 발생기는 전원전압(3.3V)부터 접지까지 출력 진폭의 범위를 갖는 1.2MHz의 주파수를 생성하며, 비교기는 2단 증폭기로 설계되었다. 그리고 오차 증폭기는 70dB의 이득과 $64^{\circ}$의 위상여유를 갖도록 설계하였다. 또한 제안한 Buck 컨버터는 current-mode PWM 제어회로와 낮은 온 저항을 갖는 스위치를 사용하여 100mA의 출력 전류에서 최대 95%의 효율을 구현하였으며, 1mA 이하의 대기모드에도 높은 효율을 구현하기 위하여 LDO 레귤레이터를 설계하였으며, 또한 2개의 IC 보호 회로를 내장하여 신뢰성을 확보하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• 한국연초학회지
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• 제27권1호
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• pp.11-18
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• 2005

The nicotine converter genotypes of burley tobacco (Nicotiana tabacum L.), which convert nicotine to nornicotine, contain a high amount of nornicotine that degrades tobacco quality and smoking taste. Elimination of nicotine converter plants before seed harvesting is required for breeding nicotine low-converter lines and for increasing their seed production. This study aims to develop a rapid and convenient method of identifying nicotine converter plants of burley breeding lines of KB9118(KB108) using thin-layer chromatography (TLC) and isatin coloration method. Out of 223 plants in 10 lines harvested at maturity in 2002, 102 plants ($45\%$) were identified as nicotine converters by TLC of tobacco leaves air-cured. For 16 lines selected as low-converters in 2002, 148 plants grown in the field in 2003 were tested by the isatin coloration method using two detached leaves at the flowering stage thoroughly sprayed with $1\%\;NaHCO_3$ solution and cured in conditioned chambers for the early identification of nicotine to nornicotine conversion. From these samples, 46 plants ($31\%$) in 4 lines were identified as nicotine converters, indicating that the ratio of converters significantly decreased by one time selection. Mean percent conversion of non-screened lines was $14\%$ higher than that of following generation. Therefore in the burley tobacco, a rapid and convenient means of identifying and removing nornicotine converter plants by the isatin coloration method during growth in the greenhouse or field were effective in reducing the converter plants in the following generation.

• 전력전자학회논문지
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• 제14권6호
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• pp.449-456
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• 2009

본 논문에서는 PFC단 링크 캐패시터의 실효 전류를 크게 저감 할 수 있는 링크 캐패시터 전류 스트레스 저감기법을 제안한다. 링크 캐패시터 선정 기준에는 여러 가지가 있으나 가장 큰 비중을 차지하는 것이 캐패시터 실효전류이다. 제안된 C-L 필터는 PFC단 출력 전류를 필터링하여 링크 캐패시터의 실효 전류를 크게 줄일 수 있고, 제안된 C-L-L-C 필터는 C-L 필터의 출력 전류 필터링 효과와 함께 L-C 필터가 DC/DC단 입력 전류를 필터링 함으로써 링크 캐패시터의 실효 전류를 더욱 크게 줄일 수 있다. 제안된 필터는 설계가 간단하고 PFC단의 Crossover frequency가 매우 낮아 C-L 필터 및 C-L-L-C 필터의 Cut-off frequency가 PFC단의 제어기 루프에 영향을 주지 않으므로 적은 소자를 가지고 손쉬운 방법으로 링크 캐패시터의 실효전류를 크게 줄일 수 있다. 제안된 필터의 이론적 해석과 설계 방법을 제시하며, 실험을 통하여 그 우수성을 검증한다.

• 전력전자학회논문지
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• 제21권6호
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• pp.514-524
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• 2016

This work suggests a study on 5 kW plasma power supply design and reactor capacitance estimation algorithm for a wide range of linear output control to operate a plasma reactor. The suggested study is designed to use a two-stage circuit and control the full-bridge circuit of the two-stage circuit using the buck converter output voltage of the single-stage circuit. The switching frequency of the full-bridge circuit is designed to operate through high-frequency switching and obtain maximum output using LC parallel resonance. Soft switching technique(ZVS) is used to reduce the loss caused by high-frequency switching, and duty control of the buck converter is applied to control a wide range of linear output. The internal capacitance of the reactor cannot easily be extracted, and thus, the reactor cannot be operated in an optimized resonant state. To address this issue, this work designs the internal capacitance of the reactor such that estimations can be performed with the developed reactor capacitance estimation algorithm applied to the internal capacitance of the reactor. A 5 kW plasma power supply is designed for a wide range of linear output control, and the validity of the study on the reactor capacitance estimation algorithm is verified.