• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.382-382
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• 2010

$TaO_2$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility in achieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFETchannel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. The atomic structure of amorphous and crystalline Tantalum oxide ($TaO_2$) gate dielectrics thin film on Si (100) were grown by utilizing atomic layer deposition method was examined using Ta-K edge x-ray absorption spectroscopy. By using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) the electronic and optical properties was obtained. In this study, the band gap (3.400.1 eV) and the optical properties of $TaO_2$ thin films were obtained from the experimental inelastic scattering cross section of reflection electron energy loss spectroscopy (REELS) spectra. EXAFS spectra show that the ordered bonding of Ta-Ta for c-$TaO_2$ which is not for c-$TaO_2$ thin film. The optical properties' e.g., index refractive (n), extinction coefficient (k) and dielectric function ($\varepsilon$) were obtained from REELS spectra by using QUEELS-$\varepsilon$(k, $\omega$)-REELS software shows good agreement with other results. The energy-dependent behaviors of reflection, absorption or transparency in $TaO_2$ thin films also have been determined from the optical properties.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.381-381
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• 2010

$(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility inachieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFET channel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric films on p-Si (100) were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gapswere obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of $ZrO_2$. In addition, The dielectric function (k, $\omega$), index of refraction n and the extinction coefficient k for the $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-$\varepsilon$(k, $\omega$)-REELS software package. These optical properties are similar with $ZrO_2$ dielectric thin films.

• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.125-128
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• 2023

Recently, as the process of the MOS device becomes more detailed, and the degree of integration thereof increases, many problems such as leakage current due to an increase in electron tunneling due to the thickness of SiO₂ used as a gate oxide have occurred. In order to overcome the limitation of SiO₂, many studies have been conducted on HfO₂ that has a thermodynamic stability with silicon during processing, has a higher dielectric constant than SiO₂, and has an appropriate band gap. In this study, HfO₂, which is attracting attention in various fields, was doped with Al and the change in properties according to its concentration was studied. Al-doped HfO₂ thin film was deposited using Plasma Enhanced Atomic Layer Deposition (PEALD), and the structural and electrical characteristics of the fabricated MIM device were evaluated. The results of this study are expected to make an essential cornerstone in the future field of next-generation semiconductor device materials.

• 전기화학회지
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• 제5권3호
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• pp.111-116
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• 2002

묽은 불산용액에서 Si(111) 산화막 (SiOx) 표면을 전기화학적으로 에칭할 때 생성되는 Si(111)-H 표면변화를 전기화학적 주사터널링현미경을 사용하여 조사하였다. pH가 4.7인 0.2M $NH_4F$ 용액에서 순환전압전류곡선은 순환 횟수가 증가할수록 양극 암전류가 감소하였고 두 번 이상 순환한 시료의 암전류는 일정한 형태의 전압전류곡선을 나타냈다. 이때 표면은 모든 SiOx층이 벗겨져 수소말단화된 구조를 가졌으며, 그 이후 순환에서는 생성된 Si(111)-H 표면의 이중 수소결합이 없어지는 step-flow반응이 일어나, 표면이 단일수소결합을 가지는 [112]모서리의 안정한 삼각형 모양을 나타냈으며 또한 생성된 삼각형 흠의 깊이가 점차 깊어졌다. 일정전압법에서는 초기에 큰 양극 암전류 최고 값을 나타낸 후, 시간에 따라 양극 암전류가 감소하였다. 양극 암전류 최고 값 후. 표면의 모든 SiOx가 벗겨졌으며 이후 양극 암전류는 작은 값을 띠면 조금씩 더 낮아졌다. 이 낮아지는 양극 암전류 역시 이중수소 결합의 step-How반응에 안정한 단일수소결합의 [112]모서리 생성에 의해 나타난다. pH 4.7인 0.2M $NH_4F$용액중의 Si(111)-H표면에 +0.4V를 가할 때 진행되는 에칭반응의 메커니즘에 관해서 논하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.490.2-490.2
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• 2014

Since the general solar cells accept sun light at the front side, excluding the electrode area, electrons move from the emitter to the front electrode and start to collect at the grid edge. Thus the edge of gridline can be important for electrical properties of screen-printed silicon solar cells. In this study, the improvement of electrical properties in screen-printed crystalline silicon solar cells by contact treatment of grid edge was investigated. The samples with $60{\Omega}/{\square}$ and $70{\Omega}/{\square}$ emitter were prepared. After front side of samples was deposited by SiNx commercial Ag paste and Al paste were printed at front side and rear side respectively. Each sample was co-fired between $670^{\circ}C$ and $780^{\circ}C$ in the rapid thermal processing (RTP). After the firing process, the cells were dipped in 2.5% hydrofluoric acid (HF) at room temperature for various times under 60 seconds and then rinsed in deionized water. (This is called "contact treatment") After dipping in HF for a certain period, the samples from each firing condition were compared by measurement. Cell performances were measured by Suns-Voc, solar simulator, the transfer length method and a field emission scanning electron microscope. According to HF treatment, once the thin glass layer at the grid edge was etched, the current transport was changed from tunneling via Ag colloids in the glass layer to direct transport via Ag colloids between the Ag bulk and the emitter. Thus, the transfer length as well as the specific contact resistance decreased. For more details a model of the current path was proposed to explain the effect of HF treatment at the edge of the Ag grid. It is expected that HF treatment may help to improve the contact of high sheet-resistance emitter as well as the contact of a high specific contact resistance.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.73-75
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• 2013

Atomic force microscopy (AFM) [1] can now not only image individual atoms but also construct atom letters using atom manipulation method [2]. Therefore, the AFM is the second generation atomic tool following the well-known scanning tunneling microscopy (STM). The AFM, however, has the advantages that it can image even insulating surfaces with atomic resolution and also measure the atomic force itself between the tip-apex outermost atom and the sample surface atom. Noting these advantages, we have been developing a novel bottom-up nanostructuring system, as shown in Fig. 1, based on the AFM. It can identify chemical species of individual atoms [3] and then manipulate selected atom species to the designed site one-by-one [2] to assemble complex nanostructures consisted of many atom species at room temperature (RT). In this invited talk, we will introduce our results toward atom-by-atom assembly of composite nanomaterials based on the AFM at RT. To identify chemical species, we developed the site-specific force spectroscopy at RT by compensating the thermal drift using the atom tracking. By converting the precise site-specific frequency shift curves, we obtained short-range force curves of selected Sn and Si atoms as shown in Fig. 2(a) and 2(b) [4]. Then using the atom-by-atom force spectroscopy at RT, we succeeded in chemical identification of intermixed three atom species in Pb/Sn/Si(111)-(${\surd}3$'${\surd}3$) surface as shown in Fig. 2(c) [3]. To create composite nanostructures, we found the lateral atom interchange phenomenon at RT, which enables us to exchange embedded heterogeneous atoms [2]. By combining this phenomenon with the modified vector scan, we constructed the atom letters "Sn" consisted of substitutional Sn adatoms embedded in Ge adatoms at RT as shown in Fig. 3(a)~(f) [2]. Besides, we found another kind of atom interchange phenomenon at RT that is the vertical atom interchange phenomenon, which directly interchanges the surface selected Sn atoms with the tip apex Si atoms [5]. This method is an advanced interchangeable single atom pen at RT. Then using this method, we created the atom letters "Si" consisted of substituted Si adatoms embedded in Sn adatoms at RT as shown in Fig. 4(a)~(f) [5]. In addition to the above results, we will introduce the simultaneous evaluation of the force and current at the atomic scale using the combined AFM/STM at RT.

• 화약ㆍ발파
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• 제26권2호
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• pp.38-44
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• 2008

최근에 국내의 도로건설계획은 기존도로의 선형을 개량하거나 변경하는 데에 중점을 두므로, 건설하고자 하는 도로는 보다 현재 직선화되고 있는 추세이다. 국내의 지형은 대부분 산악지로 구성되어 있어 도로선형의 직선화에 따라 많은 교량과 터널의 계획이 불가피하며, 일부 산악터널의 갱구부는 터널굴착시 작업공간이 협소한 가파른 지형을 갖는 산안 계곡에 위치하는 경우가 있다. 이와 같이 가파른 지형에 터널 갱구부 굴착시 대안으로 역방향 굴착을 들 수 있는데, 3가지의 중요한 고려사항이 있다. 첫째, 적정한 폭, 높이, 그리고 길이로 Pilot 터널을 계획하는 것이며, 둘째, 터널 갱구부의 편토압에 대한 영향을 평가하는 것이고, 셋째, 갱구부의 얕은 심도의 지반조건에 대한 터널 안전성을 확보하는 것이라고 할 수 있다. 따라서 본 연구는 3차원 수치해석에 의해 얻어진 결과를 토대로 역방향 굴착의 적정성 및 Pilot 터널의 적용 범위를 제안코자 한다. 해석결과 Pilot 터널은 터널 안쪽 $20{\sim}25m$ 지점 전부터 갱구부 쪽으로 굴착하는 것이 적정함을 보이고 있다.

• 대한전자공학회논문지SD
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• 제45권12호
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• pp.1-7
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• 2008

Magnetic Tunnel Junction (MTJ)는 비휘발성 소자로서 그간 기억소자분야에 국한되어왔으나, 최근 다양한 연구들에 의하여 자기논리 (magneto-logic) 회로에 사용되면서 기존 트랜지스터 기반의 논리연산자를 대체할 수 있는 가능성을 보이고 있으며, 논리회로까지 확장 적용되어 스핀전자공학 분야의 새로운 장을 열 것으로 기대되어지고 있다. 자체 저장 능력을 갖는 MTJ 소자로 구현된 자기논리 회로는 전원이 꺼져도 정보가 그대로 유지되고, 또한, 불 (Boolean) 연산 수행 시 단순한 입력변화만으로 다양한 논리 연산자 구현이 가능한 구조적인 유연성을 보이므로, 물리적으로 완성된 회로 내에서 얼마든지 재구성이 가능한 자기논리 회로를 구현할 수 있다. 본 논문에서는 단순한 조합논리나 순차논리 회로의 동작을 넘어서, 임의의 3비트 논리회로 동작을 모두 수행할 수 있는 자기논리 회로를 제안한다. 이를 위해 3비트 논리회로 중에서 최대의 복잡성을 갖는 논리회로를 MTJ 소자를 사용하여 설계하였고, 그 동작을 이전 논문에서 제안된 바 있는 macro-model을 보완 적용하여 검증하였다. 제안된 회로는 3비트로 구현할 수 있는 가장 복잡한 논리회로의 동작을 수행할 뿐만 아니라, 전류구동회로의 게이트 신호들을 변화시킴으로써 임의의 3비트 논리 회로의 동작을 모두 수행하는 것이 가능하다.