• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.212-214
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• 2004

In this study, we fabricated the organic thin film by self-assembly method by using nitro-group and methoxy-group organic molecule. Also, we selected the organic single molecule in organic thin film and measured current-voltage characteristics by using scanning tunneling microscopy. The Organic molecules that use in an experiment is 4,4'-(diethynylphenyl)-2'-nitro-1-benzen ethiol and 4-[2,5-dimethoxy-4-ph enylethynylphenyl]ethynylphenylethanthiol. 4,4'-(dimet hynylphenyl)-2'-nitro-1-benzenethiol is applied widely in molecular electronic device and 4-[2,5-dime thoxy-4-phenylethynylphenyl]ethynylphenylethanthiol composed in Korea Research Institute of Chemical Technology. To be confirmed the formation of the self-assembled monolayers, we observed the real time frequency shift of the QCM and investigated surface of the self-assembled monolayers the using STM. With this, we measured current to the organic single molecule, in condition of the air state. As a result, we confirmed in constant voltage that properties of negative differential resistance. Using properties of negative differential resistance to get from this study, application is expected to be molecular switching device, memory device and logic device.

• Journal of KIISE:Information Networking
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• v.30 no.1
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• pp.117-125
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• 2003

IPv6 (IP version 6), which was standardized by the IETF (Internet Engineering Task Force) to cope with existing IPv4 problems, needs several approaches for interoperation with IPv4. The internetworking of IPv6 with IPv4 is an important key to the deployment of the next generation Internet. As the solutions to the transition mechanism, both tunneling and translator methods have been proposed. In this paper, we analyze functional elements for implementation design of a transition mechanism based on the NAT-PT (NAT-Protocol Translation), and propose an extension algorithm that uses ports for effective use of global IPv4 addresses. The algorithm presented in this paper is a method of combining NAT-PT with Port Translation mechanism. The algorithm does not assign an IPv4 address to the host that needs IPv4 address, but allocates a single temporary IPv4 address and a port number in order to identify host.

• The KIPS Transactions:PartC
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• v.12C no.2 s.98
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• pp.267-280
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• 2005

In this paper, we implement and verify XMIP integrating IETF Mobile IP and the Explicit Multicast mechanism for a great number of small group multicast communications. U a source node sends Xcast packets explicitly inserting destination nodes into the headers, each Xcast router decides routes and forwards the packets toward each destination node based on unicast routing table without the support of multicast trees. n is a straightforward and simple multicast mechanism just based on a unicast routing table without maintaining multicast states because of the inheritance from the Explicit Multicast mechanism. This research modifies and extends the functionality of IETF Mobile IP's mobility agents, such as HA/FA to HA+/FA+ respectively, considering interworking with Xcast networks. Xcast packets captured by HA+ are forwarded into X-in-X tunnel interfaces for each FA+ referred to the binding table of HA.. This X-in-X tunneling mechanism can effectively solve the traffic concentration problem of IETF Mobile IP multicast services. Finally WLAN-based testbed is built and a multi-user Instant messenger system is developed as a Xcast application for finally verify the feasibility of the implemented XMIP/Xcast protocols.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.783-792
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• 2001

It is well known that, in the near future, the lifetime of the IPv4 address space will be limited and available 32-bit IP network addresses will not be left any more. In order to solve such IPv4 address space problem in an effective way, the transition to the new version using IPv6 architecture is inevitably required. At present, it is impossible to convert IPv4 into IPv6 at a time, since the coverage and the size of today's Internet is too huge. Therefore, the coexistence of both IPv4 and IPv6 must be arranged in a special and practical fashion for rapid conversion on the whole. IP protocol translation has been proposed to ease the translation of the Internet from IPv4 to IPv6. This paper presents the design and implementation of a transparent transition service that translates packet header as they cross between IPv4 and IPv6 networks. IPv4/IPv6 Translation Protocol is written in c source code and is tested by the local test recommended by ISO, which has the most excellent error detection function. The test was processed with a test scenario and it was found that the results were successful.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.721-730
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• 2001

Nowadays corporation networks are growing rapidly and they are needed to communicate with branch offices. Therefore, a VPN (Virtual Private Network) appears to reduce the cost of access and facilitate to manage and operate the enterprise network. Along with this trend, many studies have been done on VPN. It is important that the performance issues should be considered when VPN protocols are applied. However, most of them are limited on the tunneling methods and implementation of VPN and a few studies are performed on how installation of VPN affects the network. Therefore, in this paper, a testbed is constructed and VPN protocols are installed on it. Real traffic is generated and transmitted on the testbed to test how installing a VPN affects the network. As a result, layer 3 VPN protocol shows lower network performance than layer 2 VPN protocols. And we realize that the combination of L2TP and IPSec is the better method to install VPN than using IPSec only in the aspects of performance and security.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.361-361
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• 2010

The separated quasi-one-dimensional ($7{\times}7$) and ($5{\times}5$) phases on vicinal Si(557) surfaces were successfully realized by changing the crystallographic orientation and thermal treatment conditions. A small change in the crystallographic orientation of the Si(557) surface stabilized the quasi-one-dimensional ($5{\times}5$) phase of a (111) facet on vicinal Si(557) surfaces and made it coexist with a quasi-one-dimensional ($7{\times}7$) phase after an optimal thermal treatment, whereas only the quasi-one-dimensional ($7{\times}7$) phase was stable on the Si(557) surface. Interestingly, this causes the (111) terraces with different widths (L) to prefer only one of the $5{\times}5$ (L=12) and $7{\times}7$ (L=9) phases resulting in long-range order of both phases along the step edge direction, which was observed by scanning tunneling microscopy (STM) and was supported by first principle calculations. In contrast, the quasi-one-dimensional ($5{\times}5$ and ($7{\times}7$) phases were arranged randomly across the step edge direction. The change of surface morphology of vicinal Si(557) surfaces will be discussed with STM images and theoretical calculations by changing crystallographic cutting angles and thermal treatment conditions.