• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.66-67
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• 2002

Magnetic tunnel junction에서는 spin의 tunneling이 가장 기본적인 현상이기 때문에 tunnel junction의 특성은 tunnel barrier의 성질에 크게 의존한다. Tunnel barrier로는 지금까지 $Al_2$O$_3$가 주로 사용되고 있다. 하지만 $Al_2$O$_3$의 경우는 barrier height가 2-3 eV로 높기 때문에 저 저항의 tunnel junction을 형성하기 위해서는 Al의 두께가 1nm 이하로 낮아져야 한다. 따라서 이를 극복하기 위해서 $Al_2$O$_3$ 보다 낮은 barrier height를 갖는 절연막을 tunnel barrier로 사용하고자 하는 연구가 많이 진행되고 있다 (예를 들면 TaOx [1], ZrOx [2], GaOx [3], and HfOx [4]). (중략)

• Korean Journal of Materials Research
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• v.12 no.3
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• pp.200-204
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• 2002

We fabricated TMR devices which have double oxidized tunnel barrier using plasma oxidation method to form homogeneously oxidized AlO tunnel barrier. We sputtered 10 $\AA$-bottom Al layer and oxidized it by varying oxidation time for 5, 10, 20 sec. Subsequent sputtering of 13 $\AA$ - Al was performed and the matallic layer was oxidized for 120 sec. The electrical resistance changed from 700$\Omega$ to 2700$\Omega$ with increase of oxidation time, while variation of MR ratio was little spreading 27~31% which is larger than that of TMR device of ordinary single tunnel barrier. We calculated effective barrier height and width by measuring I-V curves, from which we found the barrier height was 1.3~1.5 eV, sufficient for tunnel barrier, and the barrier width(<16.2 $\AA$) was smaller than that of directly measured value by the tunneling electron microscopy. Our results may be caused by insufficient oxidation of Al precursor into $Al_2O_3$. However, double oxidized tunnel barriers were superior to conventional single tunnel barrier in uniformity and density. We found that the external magnetic field to switch spin direction of ferromagnetic layer of pinned layer breaking ferro-antiferro exchange coupling was increased as bottom layer oxidation time increased. Our results imply that we were able to improve MR ratio and tune switching field by employing double oxidized tunnel barrier process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.7-8
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• 2008

The memory characteristics of charge trap flash (CTF) with $HfO_2$ charge trap layer were investigated. Especially, we focused on the effects of tunnel barrier engineering consisted of $SiO_2/Si_3N_4/SiO_2$ (ONO) stack or $Si_3N_4/SiO_2/Si_3N_4$ (NON) stack. The programming and erasing characteristics were significantly enhanced by using ONO or NON tunnel barrier. These improvement are due to the increase of tunneling current by using engineered tunnel barrier. As a result, the engineered tunnel barrier is a promising technique for non-volatile flash memory applications.

• The Journal of Engineering Research
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• v.6 no.2
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• pp.33-38
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• 2004

To investigate the reliability of the MTJs on the roughness of insulating tunnel barrier, we prepared two MTJs with the different uniformity of barrier thickness. Namely, the one has uniform insulating barrier thickness; the other has non-uniform insulating barrier thickness as compared to different thing. As to depositing amorphous layer CoZrNb under the pinning layer IrMn, we achieved MTJ with uniform barrier thickness. Toinvestigate the reliability of the MTJs dependent on the bottom electrode, time-dependent dielectric breakdown (TDDB) measurements were carried out under constant voltage stress. The Weibull fit of out data shows clearly that $t_{BD}$ scales with the thickness uniformity of MTJs tunnel barrier. Assuming a linear dependence of log($t_{BD}$) on stress voltages, we obtained the lifetime of $10^4$years at a operating voltage of 0.4 V at MTJs comprising CoNbZr layers. This study shows that the reliabilityof new MTJs structure was improved due to the ultra smooth barrier, because the surface roughness of the bottom electrode influenced the uniformity of tunnel barrier.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• Journal of the Korean Magnetics Society
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• v.12 no.3
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• pp.99-102
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• 2002

We fabricated TMR devices which have doubly oxidized tunnel barrier using plasma oxidation method to form homogeneously oxidized AlO tunnel barrier. We sputtered 10 $\AA$-bottom Al layer and oxidized it with oxidation time of 10 sec. Subsequent sputtering of 13 $\AA$-Al was performed and the metallic layer was oxidized for 50, 80, and 120 sec., respectively. The electrical resistance changed from 500 Ω to 2000 Ω with increase of oxidation time, while variation of MR ratio was little spreading 27∼31 % which is larger than that of TMR device of ordinary single tunnel barrier. We calculated effective barrier height and width by measuring I-V curves, from which we found the barrier height was 1.3∼1.8 eV sufficient for tunnel barrier, and the barrier width (<15.0 $\AA$) was smaller than physical thickness. Our results may be caused by insufficient oxidation of Al precursor into A1$_2$O$_3$. However, doubly oxidized tunnel barriers were superior to conventional single tunnel barrier in uniformity and density. Our results imply that we were able to improve MR ratio and tune resistance by employing doubly oxidized tunnel barrier process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.159-160
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• 2012

지난 30년 동안 플래시 메모리의 주류 역할을 하였던 부유 게이트 플래시 메모리는 40 nm 기술 노드 이하에서 셀간 간섭, 터널 산화막의 누설전류 등에 의한 오동작으로 기술적 한계를 맞게 되었다. 또한 기존의 비휘발성 메모리는 동작 시 높은 전압을 요구하므로 전력소비 측면에서도 취약한 단점이 있다. 그러나 이러한 문제점들을 기존의 Si기반의 소자기술이 아닌 새로운 재료나 공정을 통해서 해결하려는 연구가 최근 활발하게 진행되고 있다. 특히, 플래시 메모리의 중요한 구성요소의 하나인 터널 산화막은 메모리 소자의 크기가 줄어듦에 따라서 SiO2단층 구조로서는 7 nm 이하에서 stress induced leakage current (SILC), 직접 터널링 전류의 증가와 같은 많은 문제점들이 발생한다. 한편, 기존의 부유 게이트 타입의 메모리를 대신할 것으로 기대되는 전하 포획형 메모리는 쓰기/지우기 속도를 향상시킬 수 있으며 소자의 축소화에도 셀간 간섭이 일어나지 않으므로 부유 게이트 플래시 메모리를 대체할 수 있는 기술로 주목받고 있다. 특히, TBM (tunnel barrier engineered memory) 소자는 유전율이 큰 절연막을 적층하여 전계에 대한 터널 산화막의 민감도를 증가시키고, 적층된 물리적 두께의 증가에 의해 메모리의 데이터 유지 특성을 크게 개선시킬 수 있는 기술로 관심이 증가하고 있다. 본 연구에서는 Si3N4/Ta2O5를 적층시킨 staggered구조의 tunnel barrier를 제안하였고, Si기판 위에 tunnel layer로 Si3N4를 Low Pressure Chemical Vapor Deposition (LPCVD) 방법과 Ta2O5를 RF Sputtering 방법으로 각각 3/3 nm 증착한 후 e-beam evaporation을 이용하여 게이트 전극으로 Al을 150 nm 증착하여 MIS- capacitor구조의 메모리 소자를 제작하여 동작 특성을 평가하였다. 또한, Si3N4/Ta2O5 staggered tunnel barrier 형성 후의 후속 열처리에 따른 전기적 특성의 개선효과를 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.8
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• pp.688-693
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• 2001

A series of Fe/CeO$_2$/Fe$_{75}$Co$_{25}$ tunnel junctions (Magnetic Tunnel Junction, MTJ) having CeO$_2$ barrier layers from 30 to 90$\AA$ in thickness were prepared by ion beam sputtering (IBS) method. In order to compare the properties of MTJs, Fe/Al oxide/Fe-Co tunnel junctions were also prepared. Some junctions with a CeO$_2$ barrier layer showed the ferromagnetic tunneling effect and the highest MR ratio at room temperature was 5%. The electric resistance of junctions with a CeO$_2$ barrier layer was higher that that of junctions with an Al oxide barrier. On the other hand, The interface analysis of the Fe/CeO$_2$ bilayer was conducted by means of X-ray photoelectron spectroscopy (XPS). It was found that CeO$_2$ was decomposed to Ce and $O_2$ during sputtering, and Fe was oxidized with these decomposed $O_2$ molecules. The reduction of both electric resistance and MR ratio may be associated with the decomposed Ce in the barrier layer.r.r.