• Journal of information and communication convergence engineering
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• v.13 no.2
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• pp.139-143
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• 2015

A push-push voltage controlled dielectric resonator oscillator (VCDRO) with a modified frequency tuning structure using broadside couplers is investigated. The push-push VCDRO designed at 16 GHz is manufactured using a low temperature co-fired ceramic (LTCC) technology to reduce the circuit size. The frequency tuning structure using a broadside coupler is embedded in a layer of the A6 substrate by using the LTCC process. Experimental results show that the fundamental and third harmonics are suppressed above 15 dBc and 30 dBc, respectively, and the phase noise of push-push VCDRO is -97.5 dBc/Hz at an offset frequency of 100 kHz from the carrier. The proposed frequency tuning structure has a tuning range of 4.46 MHz over a control voltage of 1-11 V. This push-push VCDRO has a miniature size of 15 mm×15 mm. The proposed design and fabrication techniques for a push-push oscillator seem to be applicable in many space and commercial VCDRO products.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.87-93
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• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.2
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• pp.1-9
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• 1980

A voltage synthesizing channel selection circuit was designed to improve on the conventional vol tape synthesizer which has been memorized each charnel's tuning vol cage itself. In the course of this study, tuning voltage was calculated by channel number entered from 10 keys. Then this circuit has tie function of direct access channel selection and rear display of channel number for the whole range of UHF and VHF, Attention was also given to realize the fine tuning by searching each commended channel, and the sequential selection by using 2keys, and the flash of channel indicator in case of inactive station.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.122-129
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• 2014

Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

• Proceedings of the IEEK Conference
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• summer
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• pp.218-220
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• 2004

A new wide-band VCO topology using Miller capacitance is proposed. Contrary to conventional VCO using the Miller capacitance where the variable amplifier gain is negative, the proposed VCO uses both the negative and positive variable amplifier gain to enhance the frequency tuning range significantly. The proposed VCO is simulated using HSPICE. The simulations show that 410MHz and 220MHz frequency tuning range are obtained using the negative .and positive variable amplifier gain, respectively. The tuning range of the proposed VCO is $23\%$ of the center frequency(2.8GHz). The phase noise is -104dBc/Hz at 1MHz offset by simple model. The operating current is only 3.84mA at 2.5V power supply.

• Journal of IKEEE
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• v.16 no.2
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• pp.121-126
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• 2012

In this paper, a push-push VCDRO (Voltage Controlled Dielectric Resonator Oscillator) with a modified frequency tuning structure is investigated. The push-push VCDRO designed at 16GHz is manufactured using a LTCC (Low Temperature Co-fired Ceramic) technology to reduce the circuit size. The frequency tuning structure is embedded in intermediate layer of A6 substrate by an advantage of LTCC process. Experimental results show that the fundamental frequency suppression is above 30dBc, the frequency tuning range is 0.43MHz over control voltage of 0 to 12V, and phase noise of push-push VCDRO presents a good performance of -103dBc/Hz at 100KHz offset frequency from carrier.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.266-267
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• 2006

A coupling capacitor voltage transformer (CCVT) is used in extra high voltage and ultra high voltage transmission systems to obtain the standard low voltage signal for protection and measurement. To obtain the high accuracy at the power system frequency, a tuning reactor is connected between a capacitor and a voltage transformer (VT). Thus, no distortion of the secondary voltage is generated when no fault occurs. However, when a fault occurs, the secondary voltage of the CCVT has some errors due to the transient components resulting from the fault. This paper proposes an algorithm for compensating the secondary voltage of the CCVT in the time domain. With the values of the secondary voltage of the CCVT, the secondary and the primary currents are obtained; then the voltage across the capacitor and the tuning reactoris calculated and then added to the measured secondary voltage. The proposed algorithm includes the effect of the non-linear characteristic of the VT and the influence of the ferro-resonance suppression circuit. Test results indicate that the algorithm can successfully compensate the distorted secondary voltage of the CCVT irrespective of the fault distance, the fault inception angle and the fault impedance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.938-943
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• 2008

Coupling capacitor voltage transformers(CCVTs) have been used in extra or ultra high voltage systems to obtain the standard low voltage signal for protection and measurement. For fast suppression of the phenomenon of ferroresonance, three winding CCVTs are used instead of two winding CCVTs. A tuning reactor is connected between a capacitor voltage divider and a voltage transformer to reduce the phase angle difference between the primary and secondary voltages in the steady state. Slight distortion of the secondary voltage is generated when no fault occurs. However, when a fault occurs, the secondary voltage of the CCVT has significant errors due to the transient components such as dc offset component and/or high frequency components resulting from the fault. This paper proposes an algorithm for compensating the secondary voltage of a three winding CCVT in the time domain. With the values of the measured secondary voltage of the three winding CCVT, the secondary, tertiary and primary currents and voltages are estimated; then the voltages across the capacitor and the tuning reactor are calculated and then added to the measured voltage. Test results indicate that the algorithm can successfully compensate the distorted secondary voltage of the three winding CCVT irrespective of the fault distance, the fault impedance and the fault inception angle as well as in the steady state.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.437-444
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• 2015

A high output power voltage controlled oscillator (VCO) in the U-band was implemented using a 65 nm CMOS process. The proposed VCO used a transmission line to increase output voltage swing and overcome the limitations of CMOS technologies. Two varactor banks were used for fine tuning with a 5% frequency tuning range. The proposed VCO showed small variation in output voltage and operated at 51.55-54.18 GHz. The measured phase noises were -51.53 dBc/Hz, -91.84 dBc/Hz, and -101.07 dBc/Hz at offset frequencies of 10 kHz, 1 MHz, and 10 MHz, respectively, with stable output power. The chip area, including the output buffer, is $0.16{\times}0.16mm^2$ and the maximum output power was -0.11 dBm. The power consumption was 33.4 mW with a supply voltage of 1.2-V. The measured $FOM_P$ was -190.8 dBc/Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.