• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.319-319
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• 2012

현재 폭넓게 이용되고 있는 STI (Shallow Trench Isolation) 공정에서 active edge 부분에 발생하는 기생 transistor의 subthreshold hump 특성을 제어하는 연구가 활발히 이루어지고 있다. 일반적으로 STI 공정을 이용하는 MOSFET에서 active edge 부분의 얇게 형성된 gate oxide, sharp한 active edge 형성, STI gap-fill 공정 중에 생기는 channel dopant out-diffusion은 subthreshold hump 특성의 주된 요인이다. 이와 같은 문제점을 해결하기 위해 active edge rounding process와 channel dopant compensation의 implantation을 이용하여 subthresold hump 특성 개선을 연구하였다. 본 연구는 STI 공정에 필요한 wafer와 phosphorus를 함유한 wafer를 한 chamber 안에서 auto-doping하는 방법을 이용하여 subthresold hump 특성을 구현하였다. phosphorus를 함유한 wafer에서 빠져나온 phosphorus가 STI 공정중인 wafer로 침투하여, active edge 부분의 channel dopant인 boron 농도를 상대적으로 낮춰 active edge 부분의 가 감소하고 leakage current를 증가시킨다. transistor의 channel length, gate width이고, wafer#No가 클수록 phosphorous를 함유한 wafer까지의 거리는 가까워진다. wafer #01은 hump 특성이 없고, wafer#20은 에서 심한 subthreshold hump 특성을 보였다. channel length 고정, gate width를 ~으로 가변하여 width에 따른 영향을 실험하였다. active 부분에 대한 SCM image로 확인된 phosphorus에 의한 active edge 부분의 boron 농도 감소와 gate width vs curve에서 확인된 phosphorus에 의한 감소가 narrow width로 갈수록 커짐을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.117-118
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• 2008

High-pressure deuterium annealing process is proposed and investigated for enhanced electrical and reliability properties of 512Mb DDR2 DRAM without increase in process complexity. High pressure deuterium annealing (HPDA) introduced during post metal anneal (PMA) improves not only DRAM performance but also reliability characteristics of MOSFET. Compared with a control sample annealed in a conventional forming gas, additional annealing in a high pressure deuterium ambient at $400^{\circ}C$ for 30 min decreased G1DL current and junction leakage. The improvements can be explained by deuterium incorporation at $SiO_2$/Si substrate interface near isolation trench edge.

• Journal of IKEEE
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• v.23 no.3
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• pp.756-761
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• 2019

In this paper, we propose SC-SJ(Shielding Connected-Super Junction) UMOSFET structure in which p-pillars of conventional 4H-SiC Super Junction UMOSFET structures are placed under the shielding region of UMOSFET. In the case of the proposed SC-SJ UMOSFET, the p-pillar and the shielding region are coexisted so that no breakdown by the electric field occurs in the oxide film, which enables the doping concentration of the pillar to be increased. As a result, the on-resistance is lowered to improve the static characteristics of the device. Through the Sentaurus TCAD simulation, the static characteristics of proposed structure and conventional structure were compared and analyzed. The SC-SJ UMOSFET achieves a 50% reduction in on-resistance compared to the conventional structure without any change in the breakdown voltage.