• Korean Journal of Materials Research
• /
• v.8 no.7
• /
• pp.634-640
• /
• 1998

A well- shaped trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy. The trench was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $0_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching, resulted in the well filled trench with oxide and polysilicon by subsequent deposition. The passivation layer of lateral etching was mainly composed of $SiO_xF_y$ $SiO_xBr_y$ confirmed by chemical analysis. It also affects the generation and distribution of lattice defects. Most of etch induced defects were found in the edge region of the trench bottom within the depth of 10$\AA$. They are generally decreased with the thickness of residue layer and almost disappeared below the uni¬formly thick residue layer. While the formation of crystalline defects in silicon substrate mainly depends on the incident angle and energy of etch species, the region of surface defects on the thickness of residue layer formed during trench etching.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.1
• /
• pp.1-6
• /
• 2011

We have developed the process of forming one body S-type cantilever probe in the recessed trench for fine-pitched MEMS probe card. The probe (cantilever beam and pyramid tip) was formed using Deep RIE etching and wet etching. The pyramid tip was formed by the wet etching using KOH and TMAH. The process of forming the curved probe was also developed by the wet etching. Therefore, the fabricated probe is applicable for the probe card for DRAM, Flash memory and RF devices tests and probe tip for IC test socket.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.833-836
• /
• 2005

Nano-gap trench is fabricated by the novel electrochemical etching technique using forward biased PN junction formed at the backside of the wafer. PN junction is formed using boron nitride wafer and the concentration of the boron doping is the high value of $1{\times}10^{19}$ $cm^{-3}$. The electro-chemical etching is performed in the 5% HF solution under the forward bias voltage of $1{\sim}2V$. The relationship between the etch rate of the trench and the voltage of the forward bias is investigated and the dependence of the gap for the voltage also examined. The etch rate increase from 0.027 ${\mu}m/min$ to 0.031 ${\mu}m/min$ as the value of the applied voltage increase from 1V to 2V, but the the gap is kept constant value of 40 nm.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1998.08a
• /
• pp.79.1-79
• /
• 1998

• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.1001-1003
• /
• 1998

In this paper, $Ar^+$ ion laser etching process of single/poly crystalline silicon with $CCl_{2}F_{2}$ gas is studied for MEMS applications. To investigate the effects of process parameters, laser power, gas pressure, scanning speed were varied and multiple scanning was carried out to obtain high aspect ratio. In addition, scanning width was varied to observe the trench profile etched in repeating scanning cycle. From the etching of $2.6{\mu}m$ thick polycrystalline Si deposited on insulator, trench with flat bottom and vertical side wall was obtained and it is possible to apply this results for MEMS applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.501-504
• /
• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.41-44
• /
• 2015

Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

• Journal of Korean Vacuum Science & Technology
• /
• v.2 no.2
• /
• pp.122-132
• /
• 1998

Characteristics of inductively coupled Cl2/O2 and Cl2/N2 plasmas and their effects on the formation of submicron deep trench etching of single crystal silicon have been investigated using Langmuir probe, quadrupole mass spectrometer (QMS), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM), Also, when silicon is etched with oxygen added chlorine plasmas, etch products recombined with oxygen such as SiClxOy emerged and Si-O bondings were found on the etched silicon surface. However, when nitrogen is added to chlorine, no etch products recombined with nitrogen nor Si-N bondings were found on the etched silicon surface. When deep silicon trenches were teached, the characteristics of Cl2/O2 and Cl2/N2 plasmas changed the thickness of the sidewall residue (passivation layer) and the etch profile. Vertical deep submicron trench profiles having the aspect ratio higher than 5 could be obtained by controlling the thickness of the residue formed on the trench sidewall using Cl2(O2/N2) plasmas.

• Journal of the Korean Vacuum Society
• /
• v.6 no.4
• /
• pp.364-371
• /
• 1997

Silicon trench etching has been carried out using a magnetically enhanced reactive ion etching system in HBr plasma containing He-$O_2$, $CF_4$. The changes of etch rate and etch profile, the degree of residue formation, and the change of surface chemical state were investigated as a function of additive gas flow rate. A severe lateral etching was observed when pure HBr plasma was used to etch the silicon, resulted in a pot shaped trench. When He-$O_2$, $SiF_4$ additives were added to HBr plasma, the lateral etching was almost eliminated and a better trench etch profile was obtained. The surface etched in HBr/He-$O_2/SiF_4$ plasma showed relatively low contamination and residue elements compared to the surface etched in HBr/He-$O-2/CF_4$plasma. In addition, the etching characteristics including low residue formation and chemically clean etched surface were obtained by using HBr containing He-$O_2$ or $SiF_4$ additive gases instead of $CF_4$ gas, which were confirmed by X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM) and atomic force microscopy (AFM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.10
• /
• pp.853-858
• /
• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.