• 전자공학회논문지
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• 제51권6호
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• pp.124-131
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• 2014

본 논문은 무선 개인영역네트워크 환경에서 중계 프로토콜 기능을 가진 시분할다중접속방식(TDMA)의 적응형 기저대역 중계모뎀을 설계한 내용을 기술한다. 설계한 기저대역 중계모뎀은 마스터 동기 신호에 의해 제어되며 최대 14홉의 중계 네트워크를 구성할 수 있다. 효과적인 데이터 중계 통신을 위해 단일포트 메모리에서 우선권을 사용하여 내부 버퍼 설계를 최적화하였다. 그리고 메모리 버스 제어기는 합성된 게이터 수를 최소화시킬 수 방법으로 설계하였다. 협대역 TDMA 중계 통신의 동기 기능을 구현하기 위하여 네트워크 슬롯 동기회로와 프레임 동기회로를 분리하여 게이트수를 줄였다. 이 방법을 사용하여 9만 게이트의 Xilinx FPGA XC6SLX9에서 약 37%(34,000게이트)를 사용하였다. 32비트 싱크워드를 사용한 1024비트 프레임의 통신 수신율은 약 96.4%이다. 설계된 기저대역 중계모뎀을 사용하여 14홉의 중계에서 측정한 최대전송지연시간은 230.4ms이다.

• 전기의세계
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• 제28권1호
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• 전기학회논문지
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• 제57권3호
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• pp.488-493
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• 2008

This paper represents a dual-mode type transmission technique for a high reliable narrow-band power line communication(PLC) modem, and its design and implementation of a system-on-chip(SoC). The proposed transmission technique is based on a Chirp modulation for the purpose of overcoming time variations of power line channel environments in the narrow-bandwidth of the frequency range of 95-145.5 kHz. The designed modem is fabricated utilizing a mixed 0.18 ${\mu}m$ CMOS technology. Especially, according to the power line channel environments the data transmission rate can be selectively changed into 2.5 kbps and 480 bps. The total hardware complexity of the implemented chip is about 50,000 gates, the power consumption is about 26mW, and the operating frequency is up to 5.12 MHz.

• International Journal of Control, Automation, and Systems
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• 제2권1호
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• pp.23-38
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• 2004

We proposed the infinity control principle to evaluate the Biological function. The H infinity control was applied to the Sodium (Na) ion selective gating channel on the excitable cellular membrane of the neural system. The channel opening, closing and inactivation processes were expressed by movements of three gates and one inactivation blocking particle in the channel pore. The rate constants of the channel state transition were set to be voltage dependent. The temporal changes in amounts per unit membrane area of the channel states were expressed by means of eight differential equations. The biochemical mimetic used to complete the Na ion selective channel was regarded as noise. The control inputs for ejecting the blocking particle with plugging in the channel pore were set for the active transition from inactivated states to a closed or open state. By applying the H infinity control, we computed temporal changes in the channel states, observers, control inputs and the worst case noises. The present paper will be available for evaluating the noise filtering function of the biological signal transmission system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.47-50
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• 2004

In this paper, we implement an Elliptic Curve Cryptosystem(ECC) processor for DTCP. Because DTCP(Digital Transmission Content Protection) uses GF(p), where p is a 160-bit prime integer, we design a scalar multiplier based on GF(p). The scalar multiplier consists of a modular multiplier and an adder. The multiplier uses montgomery algorithm which is implemented with CSA(Carry-save Adder) and CLA(Carry-lookahead Adder). Our new scalar multiplier has been synthesized using Samsung 0.18 um CMOS technology and the maximum operation frequency is estimated 98 MHz, with the size about 65,000 gates. The resulting performance is 29.6 kbps, that is, it takes 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• 한국통신학회논문지
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• 제8권4호
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• pp.156-163
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• 1983

旣存의 44,736Mbps 傳送路에 適用하여 컬러TV信號를 傳送할수 있는 合成信號形DPCM시스템이 設計, 構成되었다. 使用된 豫測方法은 4개의 畵素를 利用하는 旣存의 2次元豫測方法이며 5비트에 해당하는 非線形量子器가 使用되었다. 實時間處理를 위해 주로 ECL素子가 많이 使用되었다. 實驗結果를 통하여 本DPCM시스템은 旣存의 傳送路를 使用하여 TV放送信號를 CATV品質이상으로 傳送할 수 있는 能力이 있음을 確認할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.281-284
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• 2003

Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

• 전기전자학회논문지
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• 제21권3호
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• pp.256-259
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• 2017

SENT(single edge nibble transmission)는 차량에 탑재되는 다양한 센서와 ECU(electronic control unit)간의 직렬 통신 프로토콜이다. SENT는 디지털 파형을 사용하기 때문에 트랜시버 회로가 필요 없고 구조가 간단하며 가격이 저렴하여 주로 센서 내장형 통신 인터페이스로 주로 사용된다. 본 논문에서는 Verilog HDL을 이용하여 SAE J2716 규격을 만족하는 SENT 인터페이스를 설계하였다. 또한 이를 FPGA로 구현하고 테스트 보드를 제작하여 동작을 확인하였다. 0.18um 공정으로 합성하였을 때의 게이트 수는 약 2,500 게이트이다.

• 대한전자공학회논문지
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• 제26권5호
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• pp.108-116
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• 1989

본 논문은 mixed level에서 VLSI회로의 논리설계를 검증하기 위한 논리 레벨 시뮬레이터인 LOSM(LOgic SIMulatos)에 대해서 논의한다. 본논문에서는 8개의 신호값과 2개의 신호강도를 이용하여 일반소자, 기능소자, transmission게이트 그리고 tri-state 게이트의 경우 종래의 시뮬레이터$^{[5~6,9]}$보다 정확한 결과를 얻을 수 있는 모델링 방법을 제안한다. LOSIM은 rise delay와 fall delay를 사용하여 주어진 회로에 대한 타이밍 분석과 hazard 분석이 가능하다. Hazard분석 및 검출은 5상태의 신호값과 time queue를 이용한 scheduled time을 이용한다. 개발된 알고리듬은 SUN-3/160 워크그테이션상에서 C-언어를 사용하여 구현되었으며, 정적 RAM셀과 비동기 회로에 대해서 프로그램의 동작 예재로 하였다.

• Journal of Photoscience
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• 제9권2호
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• pp.317-319
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• 2002

All-optical switching has been demonstrated in bacteriorhodopsin (bR) based on nonlinear intensity induced excited state absorption. The transmission of a cw probe laser beam at 410 nm corresponding to the peak absorption of M state through a bR film is switched by a pulsed pump laser beam at 570 nm that corresponds to the maximum initial 8 state absorption. The switching characteristics have been analyzed using the rate equation approach considering all the six intermediate states (B, K, L, M, N and 0) in the bR photocycle. The switching characteristics are shown to be sensitive to life time of the M state, absorption cross-section of the 8 state at probe wavelength ($\sigma$ $\_$Bp/) and peak pump intensity. It has been shown that the probe laser beam can be completely switched off (100 % modulation) by the pump laser beam at relatively low pump powers, for $\sigma$$\_$Bp/ = O. The switching characteristics have been used to design all-optical NOT, OR, AND and the universal NOR and NAND logic gates for optical computing with two pulsed pump laser beams.