• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.446-448
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• 1995

This paper dscribes a detail simulation model with EMTP (Electro-Magnetic Transients Program) which is very effective to analyze the interaction between the ac transmission line and STATCON (static condenser). The SATCON was represented by two voltage-source converters connected in parallel and sharing an energy storage dc capacitor bank. The voltage source converters was modeled with ideal gate turn-off switches. The power system was represented by a detail generator model and a distributed tramnsmission line model for detail performance analyses. Analysis results show that the conceived simulation model is very effective to analyze the interaction between the ac transmission line and STATCON, and to evaluate the performance of STATCON.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1777-1781
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• 2011

Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the transmit and receive data using the HSPICE simulations and the actual implementation on the FPGA Data transmission characteristics were described by comparing the simulation results. Simulation and measurement criteria for point to point data transmission characteristics of wire length possible to send and receive data about the speed limits were reviewed. Measured point to point connection to send and receive signals at terminal velocity, the factors that affect the electrical noise around the wire length and showed a very important role.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.240-248
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• 2001

This paper describes the design of a space-division switch which can support a self-healing operation of 2-fiber bidirectional line switched ring in 2.5Gb/s SDH-based transmission system. The switch having a 1.25Gb/s throughput has been designed and implemented with COMPASS tool and 0.87$\mu\textrm{m}$ CMOS gate-array. The proposed switch is suitable for the quickly self-healing operations when a failure occurs in a 2-fiber bidirectional switched ring composed of ADM transmission systems. The switch is composed of an add/drop control part, a cross-point switch, a frame-phase aligner, processor interface and an unequipped data framer. The test results of the switch adapted to 2.SGb/s SDH-based transmission system, show immediate restoration when a failure occurs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1833-1839
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• 2014

In this paper, a systematic demapping algorithm for three-dimensional (3-D) lattice signal constellations is presented. The algorithm consists of decision of an octant, computation of a distance from the origin, and determination of the coordinates of a symbol. Since the algorithm can be extended systematically, it is applicable to the larger lattice constellations. To verify the algorithm, 3-D signal transmission systems with field programmable gate array (FPGA) and $Matlab^{(R)}$ are implemented. And they are exploited to carry out computer simulation. As a result, both hardware and software based systems produce almost the same symbol error rates (SERs) in an additive white Gaussian noise (AWGN) environment. In addition, the hardware based system implemented with an FPGA generates waveforms of 3-D signals and recovers the original binary sequences perfectly. Those results confirm that the algorithm and the implemented 3-D transmission system operate correctly.

• Current Optics and Photonics
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• v.3 no.6
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• pp.531-540
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• 2019

Spectral Amplitude Coding Optical Code Division Multiple Access (SAC OCDMA) is an advanced technique in asynchronous environments. This paper proposes design and implementation of a novel quantum logic gate (QLG) code, with code construction algorithm generated without following any code mapping procedures for SAC system. The proposed code has a unitary matrices property with maximum overlap of one chip for various clients and no overlaps in spectra for the rest of the subscribers. Results indicate that a single algorithm produces the same length increment for codes with weight greater than two and follows the same signal to noise ratio (SNR) and bit error rate (BER) calculations for a higher number of users. This paper further examines the performance of a QLG code based SAC-OCDMA system with NAND and direct detection techniques. BER analysis was carried out for the proposed code and results were compared with existing MDW, RD and GMP codes. We demonstrate that the QLG code based system performs better in terms of cardinality, which is followed by improved BER. Numerical analysis reveals that for error free transmission (10^-9), the suggested code supports approximately 170 users with code weight 4. Our results also conclude that the proposed code provides improvement in the code construction, cross-correlation and minimization of noises.

• The KSFM Journal of Fluid Machinery
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• v.14 no.5
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• pp.39-47
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• 2011

Flow control range of valve, which is installed on pipeline, varies according to valve type, pipe diameter, pipe length, roughness, and elevation difference of both ends of pipeline. A lot of computation efforts and knowledge are needed to estimate flow control range of valve, considering above many parameters. The table of flow control range of each valve type is presented for convenience of pipeline design engineers who must make decision of valve size and type in this study. Also the reason that butterfly valve is recommended for flow control, and gate valve is forbidden is presented via quantification and figures in this study.

• JOURNAL OF ELECTRICAL WORLD
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• s.277
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• pp.69-77
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• 2000

최근 전력설비 운용상의 여러 가지 과제에 대한 유망한 해결책으로서 파워일렉트로닉스 기기를 사용한 FACTS(Flexible AC Transmission System)가 주목을 받고 있다. 그 중에서도 자려식 변환기를 사용한 FACTS기기는 계통의 유효전력$\cdot$무효전력을 계통의 상태에 의존하지 않고 자유롭게 제어할 수 있어, 계통운용의 유연성을 비약적으로 확대할 수 있는 가능성이 있다. 미쓰비시전기는 전력기기간 계통에서의 자려식 변환기 응용의 파이어니어로서 1991년 간사이전력(주) 태산개폐소에 80Mvar SVG(전지형 무효전력발생장치)를 납품하였으며 또한 자원에너지청의 ''연계강화기술개발'' 보조사업으로 도쿄전력(주)을 비롯하여 전력회사 각사, 전원개발(주)와 (재)전력중앙연구소의 지도 하에 3단자 BTB(Back to Back) 실증시스템용으로 세계 최초의 6인치 GTO(Gate Turn-off Thyristor)를 사용한 53MVA의 자려식 변환기를 제작납품하여 수백MVA 클래스의 자려식변환기 제작기술을 확립하였다. 또한 최근에는 동사가 개발한 신소자 GCT(Gate Commutated Turn-off Thyristor)는 지금까지 대용량 자려식 변환기의 커다란 과제였던 운전손실을 반감할 수 있을 것으로 기대되고 있다. 한편 배전 분야에서는 전압변동, 고조파, 순간전압강하 등의 과제가 증가하고 있어, 미쓰비시전기는 이에 응할 수 있는 파워일렉트로닉스 기기로서 콤팩트 SVG(Static Var Generator), SSTS(Solid-state Transfer Switch), 액티브필너를 다수 납품하여 전력품질문제 해결에 공헌하고 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.107-108
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• 2005

Au and $Au/SiO_2$ nanoparticles(NPs) were synthesized by the colloidal method. The formation of Au and $Au/SiO_2$ NPs was confirmed using high resolution transmission electron microscopy (HRTEM). Synthesized solutions were deposited on Si wafer. The electrical properties of structures were measured using a semiconductor analyzer and a LCR meter. Capacitance versus voltage hysterisis curves showed the charge storage effect by Au and $Au/SiO_2$ NPs.