• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.233-238
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• 1993

In this paper, two diagnosis algorithms using the simple fuzzy, cognitive map (FCM) that is an useful qualitative model are proposed. The first basic algorithm is considered as a simple transition of Shiozaki's signed directed graph approach to FCM framework. And the second one is an extended version of the basic algorithm. In the extension, three important concepts, modified temporal associative memory (TAM) recall, temporal pattern matching algorithm and hierarchical decomposition are adopted. As the resultant diagnosis scheme takes short computation time, it can be used for on-line fault diagnosis of large scale and complex processes that conventional diagnosis methods cannot be applied. The diagnosis system can be trained by the basic algorithm and generates FCM model for every experienced process fault. In on-line application, the self-generated fault model FCM generates predicted pattern sequences, which are compared with observed pattern sequences to declare the origin of fault. In practical case, observed pattern sequences depend on transport time. So if predicted pattern sequences are different from observed ones, the time weighted FCM with transport delay can be used to generate predicted ones. The fault diagnosis procedure can be completed during the actual propagation since pattern sequences of tvo different faults do not coincide in general.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.