• 대한전자공학회논문지SD
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• 제44권11호
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• pp.109-118
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• 2007

SoC의 집적도와 동작 속도의 증가로 인하여 지연 고장 테스트의 중요성이 더욱 커지고 있다. 본 논문은 천이 지연 고장 테스트를 지원하는 개선된 IEEE 1500 래퍼 셀 구조와 IEEE 1149.1 TAP 제어기를 이용하기 위한 인터페이스 회로를 제시하고 이를 이용한 테스트 방법을 제안 한다. 제안 하는 셀 구조는 한 번의 테스트 명령어를 이용하여 상승 지연 고장 테스트와 하강 지연 고장 테스트를 연속적으로 수행 할 수 기능을 유지하면서 기존의 셀 구조에 비하여 적은 면적 오버헤드를 가지며 테스트 시간을 줄일 수 있다. 또한 다른 클럭으로 동작하는 코어에 대한 테스트를 동시에 수행 할 수 있다.

• 전자공학회논문지A
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• 제31A권6호
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• ETRI Journal
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• 제30권3호
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• 전자공학회논문지A
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• 제32A권12호
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• 전자공학회논문지A
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• 제31A권10호
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.233-238
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• 1993

In this paper, two diagnosis algorithms using the simple fuzzy, cognitive map (FCM) that is an useful qualitative model are proposed. The first basic algorithm is considered as a simple transition of Shiozaki's signed directed graph approach to FCM framework. And the second one is an extended version of the basic algorithm. In the extension, three important concepts, modified temporal associative memory (TAM) recall, temporal pattern matching algorithm and hierarchical decomposition are adopted. As the resultant diagnosis scheme takes short computation time, it can be used for on-line fault diagnosis of large scale and complex processes that conventional diagnosis methods cannot be applied. The diagnosis system can be trained by the basic algorithm and generates FCM model for every experienced process fault. In on-line application, the self-generated fault model FCM generates predicted pattern sequences, which are compared with observed pattern sequences to declare the origin of fault. In practical case, observed pattern sequences depend on transport time. So if predicted pattern sequences are different from observed ones, the time weighted FCM with transport delay can be used to generate predicted ones. The fault diagnosis procedure can be completed during the actual propagation since pattern sequences of tvo different faults do not coincide in general.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.81-90
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• 2004

유한상태기의 상태할당은 이로부터 구현되는 순차회로의 속도, 면적, 테스팅 및 소비전력에 큰 영향을 미친다. 본 논문에서는 상태변수 그룹들 사이에 상호 의존성(dependency)을 최소화하여 테스팅 및 전력소모를 개선하기 위한 m-블록 분할을 이용한 새로운 상태할당 기술을 소개한다. m-블록 분할 알고리즘에 의해 상태도로부터 상태들을 그룹으로 나누어 상태변수의 상호의존성을 줄이고, 상태천이 확률에 의해 결정된 무게인자에 따라 상태간 상태변수의 변화를 최소로하는 코드를 할당하여 상태천이시 스위칭 횟수를 줄인다. 상태변수 의존성을 줄임으로써 순차회로 사이클이 줄어들어서 부분스캔 및 테스트 생성이 용이하게 되고, 상태변수간의 스위칭 횟수를 줄임으로써 소비전력이 줄어들게 든다. 즉, 본 상태할당 기술은 서로 상반 관계에 있는 테스팅과 저전력 문제를 동시에 해결할 수 있는 새로운 기술이다. 벤치마크 회로에 대한 실험결과 기존의 방법보다 고장점검도 및 소비전력이 현저히 개선되었음을 확인하였다.