• Journal of Sensor Science and Technology
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• v.26 no.4
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• pp.292-296
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• 2017

It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, the transistor aging is emerging as a circuit designer's problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.178-181
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• 2010

An automotive IC voltage regulator which consists of one-chip based on a metal-oxide semiconductor field effect transistor (MOSFET) is investigated experimentally with three types of packaging. The closed type is filled with thermal silicone gel and covered with a plastic lid on the MOSFET. The half-closed type is covered with a plastic case but without thermal silicone gel on the MOSFET. Opened type is no lid without thermal silicone gel. In order to simulate the high temperature condition in engine bay, the operating circuit of the MOSFET is constructed and the surrounding temperature is maintained at $100^{\circ}C$. In the overshoot the maximum was mainly found at the half-closed packaging and the magnitude is dependent on the packaging type and the surrounding temperature. Also the impressed current decreased exponentially during the MOSFET operation.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.583-584
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• 2006

This paper presents transistor matching in 70 nm nMOS. To adopt radio frequency(RF) applications, the RF performance, especially the current gain cutoff frequency($f_T$), is examined experimentally through a wafer. It is proved that the RF performance variation of 70 nm nMOS is dependent to the device geometry, the total width(W). The RF performance variation of 70 nm nMOS is inversely proportional to square root of total width(W). Also, decreasing of the number of fingers($N_f$) is helpful to decrease the variation of 70 nm nMOS.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1121-1126
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• 2003

In this paper we show impulse generator which is important component in UWB communication. There is two steps to generate monocycle impulse. In first step, Gaussian pulse was made by operation of transistor switching and operation time of transistor switching. The second step the high pass filter change from Gaussian to Monocycle impulse. The result of this impulse generator is impulse whose pulse width is 0,9 ns in time domain and amplitude is +/-250 ㎷.

• Carbon letters
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• v.13 no.1
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• pp.17-22
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• 2012

Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.506-507
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• 2008

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel device was width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.04b
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• pp.12-13
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• 2008

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.