• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.271-281
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• 2013

In order to improve the performance of analysis, it is important to consider the nonlinearity in power system. The Carleman embedding technique (linearization procedure) provides an effective approach in reduction of nonlinear systems. In the approach, a group of differential equations in which the state variables are formed by the original state variables and the vector monomials one can build with products of positive integer powers of them, is constructed. In traditional Carleman linearization technique, the tensor matrix is truncated to form a square matrix, and then regular linear system theory is used to solve the truncated system directly. However, it is found that part of nonlinear information is neglected when truncating the Carleman model. This paper proposes a new approach to solve the problem, by combining the Poincar$\acute{e}$ transformation with the Carleman linearization. Case studies are presented to verify the proposed method. Modal analysis shows that, with traditional Carleman linearization, the calculated contribution factors are not symmetrical, while such problems are avoided in the improved approach.

• JOURNAL OF ELECTRICAL WORLD
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• no.10 s.118
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• pp.35-39
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• 1986

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.549-553
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• 1999

This paper describes a design method of grid-connected photovoltaic power generation systems with three phase inverter. A 3-phase 50kW photovoltaic power generation system including a DC/AC inverter is designed and made in order to investigate the system performance for grid connection. Also the control scheme of a three phase current-controlled PWM inverter is presented by using d-q transformation. The experimental waveforms show that the proposed system has stable behavior with an unit power factor in utility-interactive operation.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1303-1314
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• 2019

This paper studies the harmonic characteristics of ship electric propulsion systems and their treatment methods. It also adopts effective measures to suppress and prevent ship power systems from affecting ship operation due to the serious damage caused by harmonics. Firstly, the harmonic characteristics of a ship electric propulsion system are reviewed and discussed. Secondly, aiming at problems such as resonant frequency and filter characteristics variations, resonance point migration, and unstable filtering performances in conventional passive filters, a method for fully tuning of a passive dynamic tunable filter (PDTF) is proposed to realize harmonic suppression. Thirdly, to address the problems of the uncontrollable inductance L of traditional air gap iron core reactors and the harmonics of power electronic impedance converters (PEICs), this paper proposes an electromagnetic coupling reactor with impedance transformation and harmonic suppression characteristics (ECRITHS), with the internal filter (IF) designed to suppress the harmonics generated by PEICs. The ECRITHS is characterized by both harmonic suppression and impedance change. Fourthly, the ECRITHS is investigated. This investigation includes the harmonic suppression characteristics and impedance transformation characteristics of the ECRITHS at the fundamental frequency, which shows the good performance of the ECRITHS. Simulation and experimental evaluations of the PDTF are carried out. Multiple PDTFs can be configured to realize multi-order simultaneous dynamic filtering, and can effectively eliminate the current harmonics of ship electric propulsion systems. This is done to reduce the total harmonic distortion (THD) of the supply currents to well below the 5% limit imposed by the IEEE-519 standard. The PDTF also can eliminate harmonic currents in different geographic places by using a low voltage distribution system. Finally, a detailed discussion is presented, with challenges and future implications discussed. The research results are intended to effectively eliminate the harmonics of ship electric power propulsion systems and to improve the power quality of ship power systems. This is of theoretical and practical significance for improving the power quality and power savings of ship power systems.

• Journal of Power Electronics
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• v.9 no.2
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• pp.224-231
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• 2009

The induction motor rotor fault diagnosis system using current signals, which are measured using an axis-transformation method, is presented in this paper. In inverter-fed motor drives, unlike line-driven motor drives, the stator currents are rich in harmonics; therefore fault diagnosis using stator current is not trivial. The current signals for rotor fault diagnosis need precise and high resolution information, which means the diagnosis system demands additional hardware such as a low pass filter, high resolution ADC, and encoder, etc. The proposed axis-transformation method with encoder and without encoder is expected to contribute to a low cost fault diagnosis system in inverter-fed motor drives without the need for any additional hardware. In order to confirm the validity of the developed algorithms, various experiments for rotor faults are tested and the line current spectrum of each faulty situation using Park transformation is compared with the results obtained from fast Fourier transforms.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1157-1160
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• 2003

We proposed a study on optimal clock period selection algorithm for low power RTL design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm.

• Journal of Power Electronics
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• v.2 no.2
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• pp.95-103
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• 2002

The paper deals with the control of the synchronous reluctance machine without position senser. A method for the computation of the transformation angle out of terminal voltages and currents is presented. The injection of test signals allows operation at zero speed. Fundamental for this control scheme is the angle estimation method over the whole operating range including field-weakening is discussed in detail. The implementation of the angle estimation method in a rotor-oriented control scheme and practical results are demonstrated.

• Plant Biotechnology Reports
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• v.5 no.2
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• pp.157-167
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• 2011

In order to establish a reliable and highly efficient method for genetic transformation of pepper, a monitoring system featuring GFP (green fluorescent protein) as a report marker was applied to Agrobacteriummediated transformation. A callus-induced transformation (CIT) system was used to transform the GFP gene. GFP expression was observed in all tissues of $T_0$, $T_1$ and $T_2$ peppers, constituting the first instance in which the whole pepper plant has exhibited GFP fluorescence. A total of 38 T0 peppers were obtained from 4,200 explants. The transformation rate ranged from 0.47 to 1.83% depending on the genotype, which was higher than that obtained by CIT without the GFP monitoring system. This technique could enhance selection power by monitoring GFP expression at the early stage of callus in vitro. The detection of GFP expression in the callus led to successful identification of the shoot that contained the transgene. Thus, this technique saved lots of time and money for conducting the genetic transformation process of pepper. In addition, a co-transformation technique was applied to the target transgene, CaCS (encoding capsaicinoid synthetase of Capsicum) along with GFP. Paprika varieties were transformed by the CaCS::GFP construct, and GFP expression in callus tissues of paprika was monitored to select the right transformant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.