• Title/Summary/Keyword: Tracking ADC

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A Study of Whiter Matter Fiber Tractography in Young Internet Addiction Disorder using a Brain Diffusion Tensor Magnetic Resonance Imaging (뇌 확산텐서 자기공명영상을 이용한 청소년 인터넷 중독자의 백질 섬유로에 관한 연구)

  • Goo, Eun-Hoe
    • Journal of the Korean Society of Radiology
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    • v.10 no.1
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    • pp.7-13
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    • 2016
  • The goal of this study is to investigate corpus callosum and both internal capsule changes with the internet addiction disorder compared to control group using MR diffusion tensor imaging. A total of 22 teenager volunteers who had 10 high-risk group with internet addiction and 12 normal control group were conducted for this study. Imaging was conducted on a 3 T using a EPI sequence. Image evaluation was analysed of the FA, ADC($10^{-3}mm^2/s$), length(mm). We did select ROI for image tracking on corpus callosum of 5 and including 2(internal capsule). The data from these ROIs were compared statistically among the groups using independent t-test, correlation coefficient. There were significant inter-group differences(p<0.05) among FA, ADC($10^{-3}mm^2/s$) and length(mm). And also significantly negative correlations were fond between FA values of corpus callosum and IAD scale(p=0.000). DTI was shown significant changes of FA and ADC, LNF values in IAD compared to control group. Therefore, our results may provided clinical information for brain wite matter functions.

A Design of Gate Driver Circuits in DMPPT Control for Photovoltaic System (태양광 분산형 최대전력점 추적 제어를 위한 고전압 게이트 드라이버 설계)

  • Kim, Min-Ki;Lim, Shin-Il
    • Journal of Korea Society of Industrial Information Systems
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    • v.19 no.3
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    • pp.25-30
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    • 2014
  • This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

Extracting Predominant Melody from Polyphonic Music using Harmonic Structure (하모닉 구조를 이용한 다성 음악의 주요 멜로디 검출)

  • Yoon, Jea-Yul;Lee, Seok-Pil;Seo, Kyeung-Hak;Park, Ho-Chong
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.5
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    • pp.109-116
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    • 2010
  • In this paper, we propose a method for extracting predominant melody of polyphonic music based on harmonic structure. Since polyphonic music contains multiple sound sources, the process of melody detection consists of extraction of multiple fundamental frequencies and determination of predominant melody using those fundamental frequencies. Harmonic structure is an important feature parameter of monophonic signal that has spectral peaks at the integer multiples of its fundamental frequency. We extract all fundamental frequency candidates contained in the polyphonic signal by verifying the required condition of harmonic structure. Then, we combine those harmonic peaks corresponding to each extracted fundamental frequency and assign a rank to each after calculating its harmonic average energy. We finally run pitch tracking based on the rank of extracted fundamental frequency and continuity of fundamental frequency, and determine the predominant melody. We measure the performance of proposed method using ADC 2004 DB and 100 Korean pop songs in terms of MIREX 2005 evaluation metrics, and pitch accuracy of 90.42% is obtained.

A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

Radar Signal Processor Design Using FPGA (FPGA를 이용한 레이더 신호처리 설계)

  • Ha, Changhun;Kwon, Bojun;Lee, Mangyu
    • Journal of the Korea Institute of Military Science and Technology
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    • v.20 no.4
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    • pp.482-490
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    • 2017
  • The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc.

Separation Inverter Noise and Detection of DC Series Arc in PV System Based on Discrete Wavelet Transform and High Frequency Noise Component Analysis (DWT 및 고주파 노이즈 성분 분석을 이용한 PV 시스템 인버터 노이즈 구분 및 직렬 아크 검출)

  • Ahn, Jae-Beom;Jo, Hyun-Bin;Lee, Jin-Han;Cho, Chan-Gi;Lee, Ki-Duk;Lee, Jin;Lim, Seung-Beom;Ryo, Hong-Je
    • The Transactions of the Korean Institute of Power Electronics
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    • v.26 no.4
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    • pp.271-276
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    • 2021
  • Arc fault detector based on multilevel DWT with analysis of high-frequency noise components over 100 kHz is proposed in this study to improve the performance in detecting serial arcs and distinguishing them from inverter noise in PV systems. PV inverters generally operate at a frequency range of 20-50 kHz for switching operation and maximum power tracking control, and the effect of these frequency components on the signal for arc detection leads to negative arc detection. High-speed ADC and multilevel DWT are used in this study to analyze frequency components above 100 kHz. Such high frequency components are less influenced by inverter noise and utilized to detect as well as separate DC series arc from inverter noise. Arc detectors identify the input current of PV inverters using a Rogowski coil. The sensed signal is filtered, amplified, and used in 800kSPS ADC and DWT analysis and arc occurrence determination in DSP. An arc detection simulation facility in UL1699B was constructed and AFD tests the proposed detector were conducted to verify the performance of arc detection and performance of distinction of the negative arc. The satisfactory performance of the arc detector meets the standard of arc detection and extinguishing time of UL1699B with an arc detection time of approximately 0.11 seconds.

Development of Galileo E1B-BOC(1,1) Signal Software Receiving Program (Galileo E1B신호 소프트웨어 수신프로그램 개발)

  • Jeon, Sang-Hoon;So, Hyoung-Min;Kim, Chang-Ho;Kee, Chang-Don;Cho, Young-Soo;Choi, Wan-Sik
    • Journal of Advanced Navigation Technology
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    • v.12 no.6
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    • pp.574-582
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    • 2008
  • This paper shows the research about the development of software receiver processing Galileo E1B signal. it is introduced the structure of Galileo receiving software using sampled IF data as a program input. And the performance of SDR(Software Defined Radio) embodied using MATLAB tool is analyzed. Embodied SDR is modulated according to their roll and function.

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Design and Applications of a Generalized Software-Based GNSS IF Signal Generator

  • Lim, Deok-Won;Park, Chan-Sik;Lee, Sang-Jeong
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.211-215
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    • 2006
  • In this paper, design and applications of a generalized, versatile and customizable IF signal generator that can model the modernized GPS and Galileo signal is given. It generates IF sampled data that can be directly used by a software receiver. Entire constellation of satellites which is independent of satellite-user geometry is easily determined using a real or simulated ephemeris data. Since the IF center frequency, sampling frequency and quantization bit number are user location dependent parameters, their effects are also considered in IF signal generator. The generalized IF signal generator will be very well suited for the development phase of a software receiver due to its versatility. The full access to the sampling frequency, front-end filter definition and ADC parameters also offers a great opportunity for cost-effective analysis of tracking loops and error mitigation techniques at the receiver level. Interference sources can be easily added to the generator to simulate specific environments. This software IF signal generator can also be used to feed a multi-frequency multi-system software receiver for the prototyping of a combined GPS/Galileo receiver. The test result using the generated signals and a real software receiver shows the effectiveness of the implemented IF signal generator.

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Quantitative Evaluation of the Corticospinal Tract Segmented by Using Co-registered Functional MRI and Diffusion Tensor Tractography (정상인에서 기능적 뇌 자기공명영상과 확산텐서영상 합성기법을 이용한 피질척수로의 위치에 따른 정량적 분석)

  • Jang, Sung-Ho;Hong, Ji-Heon;Byun, Woo-Mok;Hwang, Chang-Ho;Yang, Dong-Seok
    • Investigative Magnetic Resonance Imaging
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    • v.13 no.1
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    • pp.40-46
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    • 2009
  • Purpose : The purpose of this study was to investigate the quantitative evaluation of the corticospinal tract (CST) at the multiple levels by using functional MRI (fMRI) co-registered to diffusion tensor tractography (DTT). Materials and Methods : Ten normal subjects without any history of neurological disorder participated in this study. fMRI was performed at 1.5 T MR scanner using hand grasp-release movement paradigm. DTT was performed by using DtiStudio on the basis of fiber assignment continuous tracking algorithm (FACT). The seed region of interest (ROI) was drawn in the area of maximum fMRI activation during the motor task of hand grasp-release movement on a 2-D fractional anisotropy (FA) color map, and the target ROI was drawn in the cortiocospinal portion of anterior lower pons. We have drawn five ROIs for the measurement of FA and apparent diffusion coefficient (ADC) along the corona radiata (CR) down to the medulla. Results : The contralateral primary sensorimotor cortex (SM1) was mainly found to be activated in all subjects. DTT showed that tracts originated from SM1 and ran to the medulla along the known pathway of the CST. In all subjects, FA values of the CST were higher at the level of the midbrain and posterior limb of internal capsule (PLIC) than the level of others. Conclusion : Our study showed that co-registered fMRI and DTT has elucidated the state of CST on 3-D and analyzed the quantitative values of FA and ADC at the multiple levels. We conclude that co-registered fMRI and DTT may be applied as a useful tool for clarifying and investigating the state of CST in the patients with brain injury.

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