• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.12
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• pp.3159-3174
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• 1994

A simple octree encoding algorithm based on a tetrahedron root has been developed to be used for fully automatic generation of three dimensional finite element meshes. This algorithm starts octree decomposition from a tetrahedron root node instead of a hexahedron root node so that the terminal mode has the same topology as the final tetrahedral mesh. As a result, the terminal octant can be used as a tetrahedral finite element without transforming its topology. In this part(I) of the thesis, an efficient algorithm for the tetrahedron-based octree is proposed. For this development, the following problems have been solved, : (1) an efficient data structure for storing the octree and finite elements, (2) an encoding scheme of a tetrahedral octree, (3) a neighbor finding technique for the tetrahedron-based octree.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of the Korea Society for Simulation
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• v.13 no.3
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• pp.43-54
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• 2004

Studies of Internet algorithms or policies require experiments on the real large-scale networks. But practical problems with large real networks make them difficult. Instead many researchers use simulations on the Internet topology models. So, It is Important that study about topology model that reflect characteristic of the internet exactly. We propose new topology model which reflect of hierarchical network and addition, removal of nodes and accompanied change of topologies. In the modeling scheme for network generation, we applied DEVS formalism and analyzed the topologies generated by our algorithms.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.4
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• pp.219-226
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• 2019

One of the most widely studied protocols for tactical ad-hoc networks is Optimized Link State Routing Protocol (OLSR). As for OLSR research, most research work focus on reducing control traffic overhead and choosing relay point. In addition, because OLSR is mostly dependent on link detection and propagation, dynamic Hello timer become research challenges. However, different timer interval causes imbalance of link validity time by affecting link lifetime. To solve this problem, we propose a weighted topology graph model for constructing a robust network topology based on the link validity time. In order to calculate the link validity time, we use control message timer, which is set for each node. The simulation results show that the proposed mechanism is able to achieve high end-to-end reliability and low end-to-end delay in small networks.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1030-1034
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• 1993

A converter topology which is capable of four-quadrant(motoring and generation) operation is proposed for the variable speed constant frequency(hereafter referred as VSCF) power conversion scheme. The new converter topology for the VSCF power conversion scheme is made of two functional stages. One is converting stage which consists of six switches and six diodes and it interfaces a three-phase 60Hz at supply and a single-phase variable-frequency ac source. The other is the commutating stage though which each phase-winding is energized.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.4
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• pp.466-472
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• 2013

The paper presents a novel DC grid connection topology and control strategy for doubly-fed induction generator (DFIG) based wind power generation system. In order to achieve the wind power conversion, the stator side converter and the rotor side converter is used to implement the DFIG control based on the indirect air-gap flux orientation, and a DC/DC converter is used for the DFIG system to DC grid connection. The maximum power point tracking and DC voltage droop control can also be implemented for the proposed DFIG system. Finally, a 4-terminal DFIG-based multi-terminal DC grid system is developed by Matlab to validate the availability of the proposed system and control strategy.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.91-93
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• 2020

In recently days using distributed power generation systems constructed with boost type dc-dc converters is being extremely popularized because of the rising need of environment friendly energy generation power systems. In this paper a new constructed An efficient Step-Up DC-DC Converter for DC Grid Applications s proposed to boost a low level DC voltage(36-80V) to high DC bus (380V) level. When comparing to other step-up converters, the proposed topology has a reduced number of switching devices, can make high quality power with lower input current ripple and has wider input DC voltage range. Finally, the performance of the proposed topology is presented by simulation results with 350W hardware prototype.

• The KIPS Transactions:PartB
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• v.17B no.1
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• pp.79-84
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• 2010

Matching spots between two sets of 2-dimensional electrophoresis can make it possible to find out the generation, extinction and change of proteins. Generally protein spots are separated by 2-dimensional electrophoresis. This process makes the position of the same protein spot a little different according to the status of the tissue or the experimental environment. Matching the spots shows that the relation of spots is non-uniform and non-linear transformation. However we can also find that the local relation preserves the topology. This study proposes a matching method motivated by the preservation of the topology. To compare the similarity of the topology, we compared the distance and the angle between neighbour spots. Experimental result shows that the proposed method is effective.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.374-376
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• 1997

This paper presents a 3kW grid-connection photovolatic power generation system and its simple topology. The system controlled by single chip micropocessor.