• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.2
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• pp.84-91
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• 2014

This paper introduces the application of supervisory monitoring system for substation automation based on IEC 61850. The objective of proposed system is detection of such a malfunction or degradation of devices. The supervisory monitoring procedure consists of a two step - topology processor and state estimation. The topology processor using artificial intelligence is a preprocessing step of state estimation. Topology processor identifies the topology structure of switches in substation and detects an error of ON/OFF state data. The state estimation is an algorithm that minimizes an error between optimal estimation values and real values. The proposed system is applied to standard digital substation based on IEC 61850 for performance verification.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.646-647
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• 2007

The topology processor uses the status of circuit breakers as input. It operates on the bus section connectivity data, which is stored in the data base, to determine the bus/branch topology of the network. This output of the topology processor forms part of the input to the state estimation or dispatcher power flow. This paper describes the development of the topology processor using matrix structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1128-1133
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• 2008

Context-aware computing has been attracting the attention as an approach to alleviating the inconvenience in human-computer interactions. This paper proposes a context-aware system architecture to be implemented on an UoC (Ubiquitous system on Chip). A new proposed technology of CRS (Context Recognition Switch) and DOS (Dynamic and Optimal Standard) based on Context-awareness system architecture with pre-processor, HPSP(High Performance Signal Processor) in this paper. And proposed a new algorithm using in network topology processor shows for Ubiquitous Computing System. implementing in UoC (Ubiquitous System on Chip) base on the IEEE 802.15.4 WPAN (Wireless Personal Area Network) standard. Also, This context-aware based UoC architecture has been developed to apply to mobile intelligent robots which would support human in a context-aware manner.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.1
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• pp.28-40
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• 1988

Nowadays, the needs for intelligence of communication equipments and the cost down of micro processor are showing a tendency to have multi0processor in a single system. In this paper, based on the Reserved Bus Topology which is propoed in "A study on he Communication Method between the adjacent processor", the software and hardware is designed and developed. And tha validity of this method and the utility of designed software and hardware functions are also verified through exepriments.epriments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.2
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• pp.1-10
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• 2010

Mapping virtual process topology to physical processor topology is one of the most important design issues in parallel programming. However, the mapping problem is complicated due to the topology irregularity and routing complexity. This paper proposes a new process mapping scheme called adjacency-based mapping (AM) for irregular cluster systems assuming that the two-dimensional mesh process topology is specified as an interprocess communication pattern. The cluster systems have been studied and developed for many years since they provide high interconnection flexibility, scalability, and expandability which are not attainable in traditional regular networks. The proposed AM tries to map neighboring processes in virtual process topology to adjacent processors in physical processor topology. Simulation study shows that the proposed AM results in better mapping quality and shorter interprocess latency compared to the conventional approaches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1276-1280
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• 2009

This paper presents a fault diagnosis expert system for 765kV substation. The proposed system includes the topology processor and intelligent alarm processing subsystems. This expert system estimates the fault section through the inference process using heuristic knowledge and the output of topology processor and intelligent alarm processing system. The rule-base of this expert system is composed of basic rules suggested by Korea Electric Power Corporation and heuristic rules. This expert system is developed using PROLOG language. Also, user friendly Graphic User Interface is developed using visual basic programming in the windows XP environment. The proposed expert system showed a promising performance through the several case studies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1045-1054
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• 2006

In this paper, described a design result of bus interface modulo for multiple level MU-SID-1553 data bus network. In general, MIL-SID-1553 network is used for single level data bus topology. But, according to applied system's structure. multiple level bus architecture is required., And for his, micro processor must be involved for system be, and a additional hardware and software functions are needed. The designed data bus interface module is simply consists of communication transceivers and simple electronic circuit without micro processor. Through the hardware testing and software simulation, the functional performance of the designed interface module was successfully validated.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.5
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• pp.19-32
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• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.21-22
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• 2007

Topology processing is indispensable basic function as it generate a real-time BUS-BRANCH model in Energy Management Systems because most application softwares such as state estimation, power flow, etc., require BUS-BRANCH circuit data. This paper propose an expert system to generate BUS-BRANCH circuit model using Artificial Intelligence technology and it is applied to 154kV distribution substations.