• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.6
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• pp.1175-1180
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• 2022

STI has been studied a lot as a process technology for wide area planarization according to miniaturization and high integration of semiconductor devices. In this study, as methods for improving the STI profile, wet etching of pad oxide using hydrofluorine solution and dry etching of O₂+CF₄ after STI dry etching were proposed. This process technology showed improvement in profile imbalance and leakage current between patterns according to device density compared to the conventional method. In addition, as a result of measuring the HLD thickness after CMP for a device having the same STI depth and HLD deposition, the measured value was different depending on the device density. It was confirmed that this was due to the difference in the thickness of the nitride film according to the device density after CMP and the selectivity of the slurry.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.620-621
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• 2008

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.

• Ocean and Polar Research
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• v.32 no.3
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• pp.299-307
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• 2010

In conjunction with geochemical characteristics, rate of sulfate reduction was investigated at two sediment sites in the continental slope and rise (basin) of the Ulleung Basin in the East Sea. Geochemical sediment analysis revealed that the surface sediments of the basin site (D2) were enriched with manganese oxides (348 ${\mu}mol$ $cm^{-3}$) and iron oxides (133 ${\mu}mol$ $cm^{-3}$), whereas total reduced sulfur (TRS) in the solid phase was nearly depleted. Sulfate reduction rates (SRRs) ranged from 20.96 to 92.87 nmol $cm^{-3}$ $d^{-1}$ at the slope site (M1) and from 0.65 to 22.32 nmol $cm^{-3}$ $d^{-1}$ at the basin site (D2). Depth integrated SRR within the top 10 cm depth of the slope site (M1; 5.25 mmol $m^{-2}$ $d^{-1}$) was approximately 6 times higher than that at the basin site (D2; 0.94 mmol $m^{-2}$ $d^{-1}$) despite high organic content (>2.0% dry wt.) in the sediment of both sites. The results indicate that the spatial variations of sulfate reduction are affected by the distribution of manganese oxide and iron oxide-enriched surface sediment of the Ulleung Basin.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Journal of Sensor Science and Technology
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• v.33 no.1
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• pp.56-61
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• 2024

The quality of the display can be managed by effectively managing the temperature generated by the panel during use. Conventional display panels rely on an external reference resistor for temperature monitoring. However, this approach is easily affected by external factors such as temperature variations from the driving circuit and chips. These variations reduce reliability, causing complicated mounting owing to the external chip, and cannot monitor the individual pixel temperatures. However, this issue can be simply and efficiently addressed by integrating temperature sensors during the display panel manufacturing process. In this study, we fabricated and analyzed a temperature sensor integrated into an a-IGZO (amorphous indium-gallium-zinc-oxide) TFT array that was to precisely monitor temperature and prevent the deterioration of OLED display pixels. The temperature sensor was positioned on top of the oxide TFT. Simultaneously, it worked as a light shield layer, contributing to the reliability of the oxide. The characteristics of the array with integrated temperature sensors were measured and analyzed while adjusting the temperature in real-time. By integrating a temperature sensor into the TFT array, monitoring the temperature of the display became easier and more accurate. This study could contribute to managing the lifetime of the display.

• Journal of IKEEE
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• v.28 no.1
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• pp.46-52
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• 2024

In this study, we investigated the electrical characteristics of SiC MOSFETs by depositing Si and oxidizing it to form the gate oxide layer. A thin Si layer was deposited approximately 20 nm thick on top of the SiC epi layer, followed by oxidation to form a gate oxide layer of around 55 nm. We compared devices with gate oxide layers produced by oxidizing SiC in terms of interface trap density, on-resistance, and field-effect mobility. The fabricated devices achieved improved interface trap density (~8.18 × 10¹¹ eV^-1cm^-2), field-effect mobility (27.7 cm²/V·s), and on-resistance (12.9 mΩ·cm²).

• Journal of the Korean Ceramic Society
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• v.55 no.6
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• pp.608-617
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• 2018

The effects of the purity and monoclinic phase of feedstock powder on the thermal durability of thermal barrier coatings (TBC) were investigated through cyclic thermal exposure. Bond and top coats were deposited by high velocity oxygen fuel method using Ni-Co based feedstock powder and air plasma spray method using three kinds of yttria-stabilized zirconia with different purity and monoclinic phase content, respectively. Furnace cyclic thermal fatigue test was performed to investigate the thermal fatigue behavior and thermal durability of TBCs. TBCs with high purity powder showed better sintering resistance and less thickness in the thermally grown oxide layer. The thermal durability was found to strongly depend on the content of monoclinic phase and the porosity in the top coat; the best thermal fatigue behavior and thermal durability were in the TBC prepared with high purity powder without monoclinic phase.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.7
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• pp.569-575
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• 2008

In this study, disk type of thermal barrier coating system for gas turbine blade was isothermally aged in the furnace changing exposure time and temperature. For each aging condition, bond tests for three samples were conducted for evaluating degradation of adhesive or cohesive strength of thermal barrier coating system. For as-sprayed condition, the location of fracture in the bond test was in the middle of epoxy which have bond strength of 57 MPa. As specimens are degraded by thermal aging, bond strength gradually decreased and the location of failure was also changed from within top coat at the earlier stage of thermal aging to the interface between top coat and TGO at the later stage due to the delamination in the coating.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.212-217
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• 2002

A new technique for highly controllable trench corner rounding at the top and bottom of the trench using pull-back and hydrogen annealing has been developed and investigated. The pull-back process could control the trench corner rounding radius at the top comers of the trench. The silicon migration generated by hydrogen annealing at the trench coiners provided (111) and (311) crystal planes and gave a uniform gate-oxide thickness, resulting in high reliable trench DMOSFETs with highly breakdown voltages and low leakage currents. The breakdown voltage of a trench DMOSFET fabricated using hydrogen annealing was increased by 25% compared with a conventional DMOSFET. The reasonable drain current of 45.3 A was obtained when a gate voltage of 10 V was supplied. The on-resistance of the trench gate DMOSFET fabricated using the trench cell of 45,000 was about 55 m(at a gate voltage of 10 V under a drain current of 5 A.