• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.375-378
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• 1995

Although laser interferometer measurement system has the advantage of range and accuracy, the traditional error measurement methods for geometric errors(two straightness and three angular errors) of a machine tool measures error components one at a time. It may also create an optical path difference and affect the measurement accuracy. In order to identify and compensate for geometric error of a moving body, an on-line measurement system for simultaneous detection of the five error components of a moving axis is required. An on-line measurement system with 5 degrees of freedom was developed for geometric error detection. Performance verification of the system was performed on an error generating mechanism. Experimental results show the feasibility of this system for identifying geometric errors of a side of machine tool.

• Journal of Computational Design and Engineering
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• v.2 no.4
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• pp.218-232
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• 2015

Piecewise linear (G01-based) tool paths generated by CAM systems lack $G_1$ and $G_2$ continuity. The discontinuity causes vibration and unnecessary hesitation during machining. To ensure efficient high-speed machining, a method to improve the continuity of the tool paths is required, such as B-spline fitting that approximates G01 paths with B-spline curves. Conventional B-spline fitting approaches cannot be directly used for tool path B-spline fitting, because they have shortages such as numerical instability, lack of chord error constraint, and lack of assurance of a usable result. Progressive and Iterative Approximation for Least Squares (LSPIA) is an efficient method for data fitting that solves the numerical instability problem. However, it does not consider chord errors and needs more work to ensure ironclad results for commercial applications. In this paper, we use LSPIA method incorporating Energy term (ELSPIA) to avoid the numerical instability, and lower chord errors by using stretching energy term. We implement several algorithm improvements, including (1) an improved technique for initial control point determination over Dominant Point Method, (2) an algorithm that updates foot point parameters as needed, (3) analysis of the degrees of freedom of control points to insert new control points only when needed, (4) chord error refinement using a similar ELSPIA method with the above enhancements. The proposed approach can generate a shape-preserving B-spline curve. Experiments with data analysis and machining tests are presented for verification of quality and efficiency. Comparisons with other known solutions are included to evaluate the worthiness of the proposed solution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Nuclear Engineering and Technology
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• v.48 no.4
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.10a
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• pp.71-76
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• 2001

In the surface measurement system using touch probe, probe radius compensation is a key factor for accuracy. In this paper we investigate methods for compensating probe radius so that the surface equation for an "unknown surface" can be efficiently derived. The developed algorithm derives the surface equation by the iterative procedure of estimation, verification, and modification . Since the procedure is applied only for the surface region exceeding the tolerance limit, an accurate surface equation can be obtained with less computation and measurement point. The validity and effectiveness of the algorithm was tested by numerical simulations. The results convinced us that the develop algorithm can be used for surface measurement and tool path planning for NC machining.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.822-826
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• 1997

근래에 들어, 금형생산 시간의 단축과 고정밀도의 제품을 생산하기 위해 실가공전의 설계단계에서 금형 데이터를 수치적으로 검증할 필요가 높아지고 있다. 기존의 저가형 CAM시스템에서 사용된 경로표시법으 로는 이러한 검증이 불가능하기 때문에 새로운 방법의 도입이 필요하며 모의가공 형상의 표현에서도 비매 개변수형 곡면을 이영하는 방법이 널리 사용되고 있다. 본 연구는 3축 금형가곡에 사용되는 볼앤드밀, 평 엔드밀 공구에 대해 Z-map을 기반으로 절삭부위를 비매개변수형 곡면으로 모델링하여 모의가공을 수행하 고자 한다. 또한, 새로운 backeting영역지정 방법을 사용하여 모의가공의 효율을 높였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.707-712
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• 1994

An Enhanced Shopfloor Oriented Programming(AESOP) system is developed as a programming utillity of the CNC turning machine. The developed system is specially designed to give a beginner the convenience for CNC part programming with graphical interaction between a machine operator and the AESOP system. The combination of process-oriented cycles and various contour programming as well as an immediate tool path verification support the easiness and swiftness of a part program generation in the shopfloor. Since the AESOP system has been designed to operate on the basis of MS-Windows in the PC-embedded CNC system, it is also useful for the training of the part programming by utilizing provailing personal computers in the educational department.

• The KIPS Transactions:PartD
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• v.14D no.5
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• pp.531-544
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• 2007

As the current trend in e-business has led to more various and complex business processes in recent years, problems in business process models have increased gradually. Accordingly, the concern to validation of business process models has been much larger but there are few validation checking mechanisms supported so far. On the other hand BPMN driven by BPMI is a standard graphical notation. Using the tool supporting BPMN, business process can be modeled graphically and analyzed easily. In this paper, we present technical mechanisms which can efficiently detect anomalies in a process composed of BPMN and are capable of avoiding higher unexpected costs during runtime.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.141-149
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• 2013

IETF 6LoWPAN standard technique has been studied in IoT environment to support the IPv6 packet communication. 6LoWPAN protocol for transmission of packets mainly in the AODV routing protocol and a variety of extended techniques have been investigated. In particular, consisting of nodes with limited resources in a network error occurs when the 6LoWPAN reliable data transfer and fast routing method is needed. To this end, in this paper, we propose resilient routing protocol and extension of IETF LOAD algorithm, for optimal recovery path, More specifically, the optimal recovery path setup algorithm, signal flow, and detailed protocols for the verification of the reliability of packet transmission mathematical model is presented. The proposed protocol techniques to analyze the performance of the NS-3 performance through the simulation results that is end-to-end delay, throughput, packet delivery fraction and control packet overhead demonstrated excellence in comparison with existing LOAD.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.407-413
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• 2015

In this paper, a DFPA(decimal floating-point adder) designed a pipeline structure that uses a LZA(leading zero anticipator) to reduce critical route to shorten delay to improve the speed of operation processing. The evaluation and verification of performance of proposed DFPA applied the Flowrian tool with simulation and Cyclone III FPGA was set as the target on the Quartus II tool for the synthesis. The proposed method compared and verified to proposed the other method using same input data. As a result, the performance of proposed method is improved 11.2% and 5.9% more than L.K.Wang's method and etc.. Also, it is confirmed that improvement of operation processing speed and reduction of the number of delay elements on critical path.