• Title/Summary/Keyword: Timing synchronization

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Symbol timing Offset Estimation for OFDM Using the 1 Symbol Offset Training Symbol and Controled CP Power (OFDM의 심벌 타이밍 옵셋 추정을 위한 1심벌 옵셋의 훈련심벌 사용법과 CP 출력조절법)

  • Ock, Youn Chul;Ha, Yeong Ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.3-13
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    • 2013
  • This paper contains two algorithms proposed for synchronization in OFDM system. The first is having 1 symbol offset while calculating the timing metric, and the second is introduced in new parameter such as Reduction Factor(${\rho}$), Break Constant(${\beta}_k$) and Implant Depth(${\delta}_I$) in order to control the power of CP(Cyclic Prefix) area. Two proposed method are evaluated performance with conventional methode, and than the result of simulation show proposed methods is better than conventional methode while it experience into multipath fading channel.

Hardware Design for Timing Synchronization of OFDM-Based WAVE Systems (OFDM 기반 WAVE 시스템의 시간동기 하드웨어 설계)

  • Huynh, Tronganh;Kim, Jin-Sang;Cho, Won-Kyung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.4A
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    • pp.473-478
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    • 2008
  • WAVE is a short-to-medium range communication standard that supports both public safety and private operations in roadside-to-vehicle and vehicle-to-vehicle communication environments. The core technology of physical layer in WAVE is orthogonal frequency division multiplexing (OFDM), which is sensitive to timing synchronization error. Besides, minimizing the latency in communication link is an essential characteristic of WAVE system. In this paper, a robust, low-complexity and small-latency timing synchronization algorithm suitable for WAVE system and its efficient hardware architecture are proposed. The comparison between proposed algorithm and other algorithms in terms of computational complexity and latency has shown the advantage of the proposed algorithm. The proposed architecture does not require RAM (Random Access Memory) which can affect the pipe lining ability and high speed operation of the hardware implementation. Synchronization error rate (SER) evaluation using both Matlab and FPGA implementation shows that the proposed algorithm exhibits a good performance over the existing algorithms.

A Study on the Firefly-Inspired Distributed Timing Synchronization in Ad Hoc Networks With Packet-Based Communications (패킷 기반 통신을 하는 애드 혹 네트워크에서 반딧불 영감을 받은 분산 타이밍 동기 연구)

  • Yi, Hyo Seok;Kim, Sungjin;Kwon, Dong-Seung;Jang, Sung-Cheol;Kim, Hyeong-Jin;Shin, Won-Yong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.3
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    • pp.575-583
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    • 2013
  • In ad hoc networks, a distributed timing synchronization is studied using a firefly-inspired approach. We illuminate the exiting synchronization algorithm based on the theory of pulse-coupled oscillators so that the algorithm can be applied to multi-carrier systems through packet-based communications, where nodes communicate over an orthogonal frequency-division multiple access air interface. As our main result, we introduce a new sync-code detector, which optimally designs both the coupling function and the detection threshold when various network parameters such as the number of nodes in the network and network topology are given a priori. Computer simulations are performed to show the convergence to a synchronized state in realistic network environments.

A Synchronization Technique for Android Multivision Applications with Multiple Smart Devices (안드로이드 기반의 다중 기기에서의 동영상 동시 재생을 위한 동기화 기법)

  • Kim, Ganghyeon;Yun, Junho;Lee, Bupjae;Kim, Daeyoung
    • Journal of KIISE
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    • v.42 no.1
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    • pp.1-6
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    • 2015
  • Smart electronics are now widely used in everyday life, but the size of the screen of such devices is still too small to fully enjoy multimedia content. Therefore, if the display is comprised of multiple views produced by multiple smart devices, then the screen output size can increase. However, a time delay between the devices can generate a discordance in the video and sound. This paper compares two synchronization techniques that can be used to minimize such a time delay, and proposes a synchronization technique in which, the timing of the screen for each device is calculated by synchronizing the playback time, using the timing information transferred from the control device, and periodically adjusting the playback timing forward or backward. When multimedia content is reproduced using multiple views from multiple smart devices, we can minimize the time delay, regardless of the network quality or the differences in the devices used for this technique.

Synchronization Sequency Design for Digital Cellular Mobile Communications (디지틀 셀룰러 이동통신을 위한 동기 부호 설계)

  • 한영일
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10A
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    • pp.1480-1485
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    • 2000
  • This paper presents an efficient synchronization sequency design for the digital cellular telephone. The class of synchronization sequences studied in this paper are sequences for synchronization that have the lowest out-of-phase values of the autocorrelation function with the two peak values equal in magnitude and opposite in polarity at zero and middle shifts. These synchronization sequences can be used to double-check synchronization timing and reduce the synchromication search time.

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Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

  • Song, Sung-Gun;Park, Seong-Mo;Lee, Jeong-Gun;Oh, Myeong-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.208-222
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    • 2015
  • For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered $0.18{\mu}m$ CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

A Symbol Synchronization Detection by Difference Method for OFDM Systems (차분방법에 의한 OFDM 심볼 동기검출 방식)

  • Joo Chang-Bok;Park Nam-Chun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.2 s.344
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    • pp.56-65
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    • 2006
  • In this paper, we introduce modified difference type symbol timing detection method of simple structure and show the relations between S/N ratio and timing detection performance which less influenced by multipath channel delay profile and added noise level and it show very exact GI detection performance characteristics. In the computer simulations, 4 symbol time duration of short and long training of IEEE802.11a standard OFDM frame are used for symbol synchronization timing detection. The computer simulation results show the very exact symbol timing detection performance characteristic within 1 sample error of OFDM signal regardless channel delay profile from minimn phase channels of phase rotation ${\pi}/2$ to non-minimum phase channels of phase rotation ${\pi}/2$ of received OFDM signal and added noise level in channel.

A Symbol Timing Recovery scheme using the jitter mean of adaptive loop filter in ATSC DTV systems (적응적 루프필터의 지터 평균값을 이용한 ATSC DTV 심볼 타이밍 동기 방식)

  • Kim, Joo-Kyoung;Lee, Joo-hyoung;Song, Hyun-keun;Kim, Jae-Moung;Kim, Seung-Won
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.10 s.340
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    • pp.1-8
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    • 2005
  • This Paper Proposes the algorithm for improving the Performance or symbol timing synchronization in hoc terrestrial DTV system. The Gardner algerian is used for symbol timing synchronization has good performance in multipath fading environment but degradation of performance is caused by jitter. Though the amount of jitter becomes more little as narrow bandwidth of loop Inter, convergence speed becomes slower. This paper propose the algorithm that averages out values of loop filter every certain time and gradually reduces the bandwidth of loop filter after estimating offset using this average for the high speed of convergence and reducing the met of jitter. The proposed algorithm has better performance with high speed of convergence and the amount of jitter than conventional method.

Complexity Reduced CP Length Pre-decision Algorithm for SSS Detection at Initial Cell Searcher of 3GPP LTE Downlink System (3GPP LTE 하향링크 시스템의 초기 셀 탐색기 SSS 검출 시 복잡도 최소화를 위한 CP 길이 선 결정 알고리즘)

  • Kim, Young-Bum;Kim, Jong-Hun;Chang, Kyung-Hi
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.9A
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    • pp.656-663
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    • 2009
  • In 3GPP LTE system downlink, PSS (primary synchronization signal) and SSS (secondary synchronization signal) sequences are used for initial cell search and synchronization. UE (user equipment) detects slot timing, frequency offset, and cell ID by using PSS. After that it should detect frame timing, cell group ID, and CP length by using SSS. But in 3GPP LTE, there are two kinds of CP length, so we should operate FFT twice. In this paper, to minimize SSS detection complexity in cell searcher, we propose a CP length pre-decision algorithm that reduces the arithmetical complexity by half at most, with negligible performance degradation.

Time Synchronization Error and Calibration in Integrated GPS/INS Systems

  • Ding, Weidong;Wang, Jinling;Li, Yong;Mumford, Peter;Rizos, Chris
    • ETRI Journal
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    • v.30 no.1
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    • pp.59-67
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    • 2008
  • The necessity for the precise time synchronization of measurement data from multiple sensors is widely recognized in the field of global positioning system/inertial navigation system (GPS/INS) integration. Having precise time synchronization is critical for achieving high data fusion performance. The limitations and advantages of various time synchronization scenarios and existing solutions are investigated in this paper. A criterion for evaluating synchronization accuracy requirements is derived on the basis of a comparison of the Kalman filter innovation series and the platform dynamics. An innovative time synchronization solution using a counter and two latching registers is proposed. The proposed solution has been implemented with off-the-shelf components and tested. The resolution and accuracy analysis shows that the proposed solution can achieve a time synchronization accuracy of 0.1 ms if INS can provide a hard-wired timing signal. A synchronization accuracy of 2 ms was achieved when the test system was used to synchronize a low-grade micro-electromechanical inertial measurement unit (IMU), which has only an RS-232 data output interface.

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