• Journal of Positioning, Navigation, and Timing
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• v.8 no.2
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• pp.49-58
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• 2019

A number of techniques have been studied to estimate the position of pedestrians in indoor space. Among them, the technique of estimating the position using only the sensors attached to the body of the pedestrian without using the infrastructure is regarded as a very important technology for special purpose pedestrians such as the firefighters. In particular, it forms a research field under the name of Pedestrian Dead Reckoning (PDR). In this paper, we focus on a method for step detection which is essential when performing PDR using Inertial Measurement Unit (IMU) mounted on a shoe. Many researches have been done to detect the stance phase where the foot contacts the ground. Most of these methods, however, have a way to detect the specific size of the sensor signal and require thresholds for these methods. This has the difficulty of changing these thresholds if the user is different. To solve this problem, we propose a stance phase detection method that does not require any threshold value. It is expected that this result will make it easier to commercialize the technology because PDR can be implemented without user-dependent parameter setting.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.305-313
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• 1999

To demodulate the received OFDM signal, symbol timing detection which finds symbol start in the received sample stream is required in the system initialization. In this paper, we analyze the effect of symbol timing offset and propose a new symbol timing detection algorithm, which is using the guard interval. The proposed algorithm requires low computational process and small memory size, and dose not be affected by frequency offset and phase offset. In addition, We apply this algorithm to European digital TV broadcasting model based on OFDM to evaluate the performance in AWGN and multipath fading channel by the computer simulation.

• Journal of Communications and Networks
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• v.14 no.5
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• pp.501-509
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• 2012

This paper proposes a joint timing synchronization, channel estimation, and data detection for the impulse radio ultra-wideband systems. The proposed timing synchronizer consists of coarse and fine timing estimation. The synchronizer discovers synchronization points in two stages and performs adaptive threshold based on the maximum pulse averaging and maximum (MAX-PA) method for more precise synchronization. Then, iterative channel estimation is performed based on the discovered synchronization points, and data are detected using the selective rake (S-RAKE) detector employing maximal ratio combining. The proposed synchronizer produces two signals-the start signal for channel estimation and the start signal for start frame delimiter (SFD) detection that detects the packet synchronization signal. With the proposed synchronization, channel estimation, and SFD detection, an S-RAKE receiver with binary pulse position modulation binary phase-shift keying modulation was constructed. In addition, an IEEE 802.15.4a channel model was used for performance comparison. The comparison results show that the constructed receiver yields high performance close to perfect synchronization.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.215-223
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• 2000

The advancements in technology which have lead to higher and higher levels of integration have required advancements in the methods used in designing VLSI chip. A key to enable a complicated chip design is the use of hierarchy in the design process. Hierarchy organizes the function of a large number of transistors ito a particular, easy-to-manage function. For these reasons, hierarchy has been used in the design process of digital functions for many years. However, there exists differences in a design analysis phase, especially in timing analysis, due to multiple views for the same design. In timing analysis of the hierarchical design, every path is analyzed within partitioned modules independently and the global timing analysis is applied to the whole design considering each module as a single timing component. Therefore, timing results of the hierarchical design could not be same as those of non-hierarchical flat design. In this paper, we formulate the timing problem in the hierarchical design and analyze the possible source of timing differences. We define a new terminology of "consistent result" between different views for the same design. We also propose a new partitioning algorithm to obtain the consistent results. This algorithm helps to enhance the design cycle time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.282-290
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• 2006

In this paper, we propose an enhanced Timing Estimator algorithm for 2.45GHz LR-WPAN receiver. Because an expensive and highly efficient oscillator can't be used for low-cost implementation, a Timing Estimator algorithm having stable operation in the channel environment with center frequency tolerance of 80 ppm is required. To enhance the robustness to frequency offset and the stability of receiver performance, multiple delay differential filter is adopted. By utilizing the characteristic that the correlation result between the output signal of Multiple delay differential filter and reference signal is restricted on the In-phase part of the correlator output, a coherent detection scheme instead of the typical noncoherent one is adopted for Timing Estimator. The application of the coherent detection scheme is suitable for LR-WPAN receiver aimed at low-cost, low-power, and low-complexity, since it can remove performance degradation due to squaring loss of I/Q squaring operation and decrease implementation complexity. Computer simulation results show that the proposed algorithm achieved performance improvement compared with the differential detection-based noncoherent scheme by 2dB in average.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.591-599
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• 2001

The paper identifies a severe form of core saturation instability in an DC/AC interaction system. It then seeks solutions to the problem by HVDC control means. This is achieved by a proper design of the Voltage Dependent Current Order Limiter (VDCOL), the Current Regulator and Timing Pulse generator. Supplementary control loops have also been introduced to result in a satisfactory performance as compared to that obtained one with the use of uncharacteristic harmonic filter on the AC side. Robustness of all the options has been demonstrated through recovery performance of the DC link in response to both I-phase and 3-phase 5 cycle faults on both rectifier and inverter commutating buses.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.227-234
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• 2014

A transceiver for a high-speed inductive-coupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a $10^{-12}$ bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.7-11
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• 2000

본 논문에서는 불완전 동기(Imperfect Synchronization)로 인한 칩 동기 에러(timing errors)와 위상 에러(phase errors)를 고려 하여 비동기(Asynchronous) DS-CDMA 시스템의 성능을 이론적으로 분석하였다. 성능 개선 기법으로는 다단 간섭제거기 (Multistage PIC)와 부분 다단 간섭제거기(Partial Multistage PIC)를 채용하였고 칩 동기 에러와 위상 에러가 두 간섭제거기의 간섭제거능력에 미치는 영향의 정도를 정량적으로 분석하였다. 성능분석 결과로부터 칩 동기 에러와 위상 에러로 인한 1단(no cancellation)에서의 성능 열화가 각 단의 상관기 출력(decision statistic)에 영향을 줌으로써 다단 간섭제거기와 부분 다단 간섭제거기의 성능 개선폭을 감소시켰다. 그렇지만, 불완전 동기에도 불구하고 단(stage) 수가 증가할수록 두 간섭제거기 모두 강한 간섭제거능력을 보였다. 실제 시스템에서는 성능 개선과 구현상의 복잡도를 동시에 고려해야하므로 다단 간섭제거기 보다 구조가 간단하고 계산량이 적은 부분 다단 간섭제거기의 활용도가 높아질 것이 예상된다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.159-160
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• 2006

We present a multiuser synchronization scheme for OFDMA uplink systems. First a new preamble structure is proposed by which timing and frequency offsets estimation is developed. Based on proposed structure a new joint synchronization scheme is presented and the simulation results show that the performance of this scheme don't suffer from the number of users.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.96-98
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• 2005

Proposed Multi-level PDP sustain Driver make use of element which has a low voltage rating instead of suggested method by the existing Webber and it passes through a second phase both rising and falling at sustaining voltage waveform In accordance with the change of timing phase(Tr1, Ti1, Tr2) performance comparison of a electric discharge characteristics in a PDP module has been carried out. At the conclusion of experimentation, the feature is extended by alteration of Ti1 and it has little to do with alteration of Tr1.