• Korean Management Science Review
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• v.11 no.1
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• pp.145-163
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• 1994

For an Information System to be successful the continual control of the database system(DBS) is very important. In general, such control operations are performed periodically in batches, even in real time systems. We explain DBS related such control operations and describe the decision problem in each of them. Specifically, backup, checkpointing, reorganization, and batch update operations are considered. Then we develop a general model of the batch backup situation to determine the optimal backup timing. Other operations are considered as special cases of the general batch backup operation are derived and compared. We show that, in general, the control limit policy is superior to the fixed time interval policy in terms of the long-run average cost per unit time. Some practical considerations about the implementation of optimal policies are also mentioned.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.137-139
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• 2006

This paper present an implementation of digital control system for a phase-shift full-bridge converter using a digital signal processor. The digital control of phase-shift full-bridge converter provides many advantageous of easily generating various phase-shift timing and implementing a complex voltage and current control algorithm. The digital controller is implemented using the DSP TMS320F2812 and the converter and controller operation is proved through the experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.365-370
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• 2002

In this paper external image multi-processing digital signal the transmit is the possibility of doing system with the PCI the design. The bottle-neck which it follows in transmission ratio limit of the CPU and the circumference machineries and tools against the image data which with the improve one thing becomes the processing with the real-time efficiently the transmit and the control is the possibility of doing structure the proposed. The also with the resource amount used 13% reduced which PCI fast data transfer and DMA function. The designed is operation verification against the function and the timing which use Max+plus II.

• ETRI Journal
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• v.36 no.3
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• pp.469-478
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• 2014

RSA signature algorithms using the Chinese remainder theorem (CRT-RSA) are approximately four-times faster than straightforward implementations of an RSA cryptosystem. However, the CRT-RSA is known to be vulnerable to fault attacks; even one execution of the algorithm is sufficient to reveal the secret keys. Over the past few years, several countermeasures against CRT-RSA fault attacks have tended to involve additional exponentiations or inversions, and in most cases, they are also vulnerable to new variants of fault attacks. In this paper, we review how Shamir's countermeasure can be broken by fault attacks and improve the countermeasure to prevent future fault attacks, with the added benefit of low additional costs. In our experiment, we use the side-channel analysis resistance framework system, a fault injection testing and verification system, which enables us to inject a fault into the right position, even to within $1{\mu}s$. We also explain how to find the exact timing of the target operation using an Atmega128 software board.

• Vacuum Magazine
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• v.1 no.1
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• pp.6-10
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• 2014

It is a common sense that water is an old offender crashing our dream of achieving a good vacuum in an early time. Various techniques for accelerating the removal of water have been developed and utilized. However, we generally are not skilled in treating the water pumping in a physically proper manner. We are rather used to handle the situation of the water pumping just like considering a conventional air pumping. Under such an erroneous approach, we cannot help making an overestimation on the pumping capability of our vacuum system, and it leads to a big mismatch between the real operation timing and the planned process schedule. In this article, some main points concerning with the subject that a vacuum pumping is really a water pumping will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• ETRI Journal
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• v.35 no.4
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• pp.710-713
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• 2013

We propose a new space-time block coding (STBC) for asynchronous cooperative systems in full-duplex mode. The orthogonal frequency division multiplexing (OFDM) transmission technique is used to combat the timing errors from the relay nodes. At the relay nodes, only one OFDM time slot is required to delay for a pair-wise symbol swap operation. The decoding complexity is lower for this new STBC than for the traditional quasi-orthogonal STBC. Simulation results show that the proposed scheme achieves excellent performances.

• KCID journal
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• v.18 no.1
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• pp.81-93
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• 2011

Agricultural reservoirs importantly role for paddy rice cultivation with about 18,000 numbers, so that understanding of operational rules for the reservoirs is quite meaningful for proper irrigation water supply. In this study, a survey was conducted to investigate a key reservoir operational elements over nationwide. The target reservoirs are mainly operated by KRC (Korea Rural Community Corporation) and 221 water management persons in province office of KRC were involved in this survey. The key reservoir operational elements including starting and ending time for irrigation, transplanting water supply periods, midsummer drainage periods and drought response strategy were surveyed. The results of this study demonstrated that the key elements for reservoir operation depend on weather, rice variety and cultivation conditions.

• Asia Marketing Journal
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• v.11 no.2
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• pp.21-35
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• 2009

In December 5, 2006, "The Economic Times", India's the most famous economy daily newspaper, reported Korea Lotte Mart is planning to enter into India's market. Lotte group, marking number 7^th in Korea's list of conglomerates, established VRIC(Vietnam, Russia, India, China)'s strategy. This strategy is targeted to enter into emerging markets such as Vietnam, Russia, India, China and etc. As of 2007, Lotte Group aggressively is placing its subsidiaries such as Lotte Department Store in Russia and China, Lotte Mart in Vietnam and China and Lotte Confectionery in China and India, into emerging markets. From this case, Based on the assumption of Lotte Mart's India market entry scenario, this study considers various decision-making factors such as market attractiveness evaluation, timing of entry, entry mode, location, scale, positioning, operation strategy, and others, while developing an overseas market entry strategy. This case study also provides India's distribution market environment that Korean companies can utilize when entering into the Indian market in the near future.