• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.5
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• pp.86-96
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• 2007

A direct-injection stratified-charge(DISC) engine has been considered as a promising alternative in spite of high unburned hydrocarbon emission levels during light load operation. In this paper investigation is made to characterize formation and combustion processes of stratified mixture charge in a simple constant volume combustion chamber. Both experimental and numerical analyses are performed for fluid and combustion characteristics with 3 different induction types for rich, homogeneous and lean mixture conditions. The commercial code FIRE is applied to the turbulent combustion process in terms of measured and calculated pressure traces and calculated distributions of mean temperature, OH radical and reaction rate. It turns out that the highest combustion rate occurs for the rich state condition at the spark ignition location due to existence of stoichiometric mixture and timing.

• Journal of the Korea Society for Simulation
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• v.10 no.4
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• pp.21-30
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• 2001

In this paper, EMI measurement, the STGU simulation being conducted, filter design, its characteristics, and its implementation to the PCB, and finally test results are discussed. When the low pass filter was implemented within the STGU, the power of EMI decreased more than 20dBm. Finally, when TE and MTIE, two important quality measure in synchronous reference clock, was assessed, ITU-T G813 requirement was satisfied. EMI(Electromagnetic Interface) is a measure of electomagnetic radiation from equipment in the range of 10KHz to 3GHz, and can cause unexpected reactions of electronics/electrical equipment. In this study, for safe and stable communication operation, a STGU (System Timing Generation Unit), which is a 2.5G SDH System and a major EMI source, was employed to simulate electromagnetic interface. Using Open-Site test, the power of fundamental frequency of EMI of interest and its harmonics were measured. Also, a low pass filter at cut-off frequency of 2GHz was specifically designed for this study to minimize the effect of EMI between electronic components.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.5
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• pp.709-717
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• 2000

Cyclic variability has long been recognized as limiting the range of operating conditions of spark ignition engines, in particular, under lean and highly diluted operation conditions. The cyclic combustion variations can be characterized by the pressure parameters, combustion parameters, and flame front parameters. The coefficient of variation in indicated mean effective pressure ($COV_{IMEP}$) defines the cyclic variability in indicated work per cycle, and it has been found that vehicle driveability problems usually result when $COV_{IMEP}$ exceeds about 10%. For analysis of the cyclic variability in SI engines at idling, the results show that cyclic variability by the $COV_{IMEP}$ or the coefficient of variation in maximum pressure can be explained and may be consequently reduced by the help of the optimum spark timings.

• Journal of Power Electronics
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• v.6 no.3
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• pp.253-263
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• 2006

A high performance and low cost single switch current fed energy recovery circuit (ERC) for an alternating current (AC) plasma display panel (PDP) is proposed. Since it is composed of only one power switch compared with the conventional circuit consisting of four power switches and two large energy recovery capacitors, the ERC features a simpler structure and lower cost. Furthermore, since all power switches can be switched under soft switching operating conditions, the proposed circuit has desirable merits such as increased reliability and low switching loss. Specifically, there are no serious voltage notches across the PDP with the aid of gas discharge current compensation, which can greatly reduce the current stress of all inverter switches, and provide those switches with the turn on timing margin. To confirm the validity of proposed circuit, its operation and performance were verified on a prototype for 7-inch test PDP.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.12
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• pp.584-589
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• 2001

This paper presents an implementation method of multi-channel synchronized phasor measurement device, which is based on the ASIC implementation of the sliding-DFT. A time-shared multiplier structure is proposed to minimize the number of gates required for the implementation. The design is verified by the timing simulation of its operation. The effect of coefficient approximation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.04a
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• pp.761-765
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• 1996

This paper describes the forging of circular tooth profiled gears as a series of development of simulator for non-axisymmetric parts that being used at the pump pulley, timing belt pulley etc. in automobiles. The half pitch of gear is divided into 6 deformation regious and kinematically admissible velocity fields for those regions are proposed. The neutral surface is introduced torepresent inner flow of material during forging operation with flat punch and, for each step, it is assumed as a circle. The upper bound solutions obtained from the suggested kinematically admissible velocity fields are in good agreement with experimental results and they are useful to predict the capacity of forging press for forging of circular gears.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• IE interfaces
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• v.11 no.2
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• pp.13-24
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• 1998

A distribution system is composed of multiple levels from a producer to customers, and it's objective is to supply customers with goods timely with a prescribed level of quality at a minimum cost. For the installation and operation of multi-echelon distribution system, DRP(Distribution Resource Planning) is widely used. However, because of the characteristic difference of material flow dynamic of each distribution center, it is almost impossible to get the optimal distribution scheduling. In this paper, an improved DRP method to schedule multi-echelon distribution network is proposed so that the lot-size and order point is dynamically obtained to meet the change of demand rate and timing. The experiment is done with various demand pattern, forecast errors of demand and lead times of central distribution center. The proposed method is compared with traditional statistical approach.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.533-536
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• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.