• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.14-17
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• 1986

In this paper, it is studied on the properties of the transmission signal for being tolerant to the timing jitter at the receiver, when an ideal low pass filter is used as the pulse shaper. A model for the transmission system with minimum bandwidth is presented and the related parameters to the tolerance or stability are explained. It has been proven that the necessary condition for a stable signaling is the same as the sufficient one.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.16-21
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• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.98-105
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• 2007

In this paper, we propose a timing detector using suboptimal maximum likelihood method. The proposed method has an simple reference signal generator. Additionally, timing detector's gain of the proposed method is the same to Early-Late gate and ML method. We reveal that tracking range of time tracker is narrow because of using data-decision, that is, tracking range is ${\pm}0.06ns$ for the 4-order Gaussian monocycle with 0.7ns pulse width. Therefore we can find that searcher must have very accurate acquisition procedure. When estimating a performance of time tracker, we consider a jitter in transmitter and receiver's pulse generation process as well as background noise. By using computer simulation, we propose mean/variance of timing detector and tracking process. Also we consider a mobility in tracking process, i.e., timing error modeled ramp function. In order to propose a performance of time tracker, we consider only one correlation demodulator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.3
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• pp.201-210
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• 1996

In this paper, we analyzed performance of a symbol timing recovery scheme for 16QAM Radio system. As a symbol timing recovery scheme, both maximum amplitude method(MAM) and wave difference method(WDM) are analyzed employing a pulse shaping filter, such as raised cosine filter(RCF) and nonlinear filter(NLF). Simulation result shows that the jitter performance of MAM or WDM using NLF is better than that using square root RCF. In order to estimate and compensate for the Rayleigh fading PSAM(Pilot Symbol Assisted Modulation) and space diversity are also employed. Consequently, BER performance of about $10^{-4}$ is obtained for $E_b/N_o$= 20 dB.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.4
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• pp.1927-1943
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• 2016

Jitterbug is a passive network covert timing channel supplying reliable stealthy transmission. It is also the basic manner of some improved covert timing channels designed for higher undetectability. The existing entropy-based detection scheme based on training sample binning may suffer from model mismatching, which results in detection performance deterioration. In this paper, a new detection method based on the feature of Jitterbug covert channel traffic is proposed. A fixed binning strategy without training samples is used to obtain bins distribution feature. Coefficient of variation (CV) is calculated for several sets of selected bins and the weighted mean is used to calculate the final CV value to distinguish Jitterbug from normal traffic. Furthermore, the timing window parameter of Jitterbug is estimated based on the detected traffic. Experimental results show that the proposed detection method can achieve high detection performance even with interference of network jitter, and the parameter estimation method can provide accurate values after accumulating plenty of detected samples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.10
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• pp.829-841
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• 1990

On assuming that the transmission speed of the original information is the fifth-order transmission speed of the Korea digital multiplex hierarchy (564.992Mb/s), this paper proposes a new structure of the transmission line frame at the terminal repeater system, in order to not only maintain and conserve 565Mb/s optical fiber transmission system but also make the B.S.I. of digital communication network for the optical transmission. And the structure uses the mBIZ transmission line code, which is considered the optimal transmission line code of conventional transmission line codes. System hardware of the transmission line frame structure proposed in this paper is consisted by a method of pulse stuffing after converting the speed of the original information signal sequence at the terminal repeater system for 565Mb/s optical transmission. As a result of this, we can prevent the optical transmission system from a domino phenomenon, the phenomenon of the continuous error multiplication of systems by the transmission error, and suppress timing jitter and the identical consecutive digit number. And also we can improve SNR of the optical transmission system about 2dB because of raising total BER at the optical terminal system up to 10.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.905-917
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• 1999

멀티미디어 시스템에서 수행되는 부하 중 상당 부분은 정해진 시간에 주기적으로 수행되어 연속 매체(continuous media)를 처리하는 주기 태스크들이다. 연속 매체들을 처리하는 두 주기 태스크의 수행 요청 시간(release time)간에 인공적인 위상(phase)을 줄 경우, 전체 부하의 처리 타이밍에 영향을 주게 되며, 특히, 적절한 위상을 부여할 경우 부하가 고르게 분산된다. 부하의 고른 분산은 태스크 간섭을 줄여 지터(jitter), 종료시한 초과(deadline miss), 그리고 긴 응답 시간(response time) 등의 문제를 해소시킨다. 본 논문에서는 새로운 위상 스케줄링(phased scheduling) 알고리즘 및 알고리즘을 개발하고 평가할 수 있는 실험 환경을 제안한다. 본 논문에 제시된 알고리즘은 저자들의 선행 논문 1 에서 제시한 알고리즘의 대안이다. 새로운 알고리즘은 정확하게 최적의 위상을 찾지는 않으나 기존 알고리즘보다 빠르게 수행되며 적용 범위가 넓다.Abstract A multimedia system consists of substantial amount of continuous media workload scheduled periodically at deterministic time points. Artificial phase between the invocation times of any two continuous media tasks affects the timing of the entire workload. A proper phase configuration distributes workload uniformly over time and reduces task interference that may otherwise result in jitter, deadline miss, and long response time. The objective of this paper is to work out a phased scheduling algorithm and to evaluate its effectiveness. The algorithm in this paper is an alternative approach to our previous work 1 . It is almost as accurate as the predecessor but two of three times faster in identifying the appropriate phase vector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.38-45
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• 2000

In this paper, an approach of modeling the optical interconnection system by SPICE simulation is presented. SPICE simulations with equivalent circuit models for optical devices are performed in a stable manner. From the simulated results, eye diagrams for receiver output and BER are obtained. Timing jitter due to laser diode turn-on delay effects can be found under various bias conditions. Using this approach, various system parameters such as bit rate, BER, dissipated transmitter power, and bias conditions can be optimized. It is expected that this approach will find useful applications such as Gigabit Ethernet and ATM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.