• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.461-464
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• 1988

In order to use mBIZ code as the practical transmission code, the information block length have to be determined. If the information block length is short, timing information disapperance is reduced, but transmission speed is increased as the result of inserted redundancy bit. While, if the information block length is long, timing information disapperance and jitter are caused. So it is very important to determine the optimal timing information block length. Therefore, in this paper, we determined the optimal information block length using S/X endurance method.

• ETRI Journal
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• v.32 no.6
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• pp.911-920
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• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.181-187
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• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1877-1883
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• 1999

Synchronization of the clock at the ATM receiving terminal is studied. The technique analyzed here has been adapted by ITU-T as the standard for ATM timing recovery. This paper presents analysis of SRTS method itself and jitter in SRTS. The power pectrum and rms amplitude of SRTS jitter are calculated. The calculated average rms value for T1 1.544MHz source signal is 32.63ns and 0.15ns for E4 139.264MHz signal.

• Journal of Advanced Navigation Technology
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• v.7 no.1
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• pp.6-13
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• 2003

In this paper, a non-coherent code tracking loop is designed for 3GPP HSDPA MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. Analytical closed-form formula for steady-state jitter variance is first derived for AWGN environments as a function of pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. Also obtained is the transient response characteristic of a tracking loop. Finally, the performance of the designed tracking loop is confirmed by computer simulations.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.565-568
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• 2000

본 논문에서는 data-driven 반향제거기 구조에서 타이밍 지터의 보상 방법을 제안한다. V.90PCM 모뎀환경에서 네트윅 클록에 동기가 되어 동작하는 사용자 터미널 모뎀이 디지털 PLL (DPLL)을 이용하여 타이밍 복원을 하면 타이밍 지터 성분이 반향제거기의 성능을 순간적으로 악화 시키게 된다. 제안된 방법은 두개의 계수세트 들로부터 타이밍 지터 발생시 필요한 계수를 디콘볼루션 알고리듬을 이용하여 FIR 필터링을 통해 구하며 발생하는 지터 성분 의 대부분을 보상 해 준다. 또한 제안 방법은 waveform driven 반향제거기에 비해 약간의 성능열화가 있지만 적은 연산량으로 타이밍 지터보상을 할 수 있는 장점이 있다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.1-11
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• 1996

In this paper, we evaluate the performance of DD-bardner (decision-directed gardner) algorithm. We derive an analytic gain of the thiming detector that is a function of SNR and an excess bandwidth, and verify the result by simulation. We also compare the DD-gardner algorithm with the bardner algorithm with respect to tracking performance and jitter performance under low SNR and a residual frequency component.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.206-209
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• 2003

본 논문에서 제안하는 알고리즘은 심벌 타이밍 jitter 를 최소화하기 위해 가장 강한 신호를 주기적으로 감시하고, 그 신호를 적응적으로 DLL(Delayed Locked Loop)의 기준 신호로 정한다. 결과적으로 제안된 알고리즘은 DLL 추적 실패를 피할 수 있고, 기존의 알고리즘에 비하여 DLL의 정상 상태 추적 오류가 작다. 모의실험을 통하여 제안된 알고리즘의 정상상태 DLL 추적오류가 작고 다중 경로 상황에서 DLL 추적 실패를 피할 수 있음을 확인 하였다. 따라서 본 논문에서 제안하는 알고리즘은 OFDM 의 시간동기 복원 알고리즘에 적합하다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1321-1326
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• 1990

In this paper, the eye-opening conditions are investigated for the minimum bandwidth digital transmission systems where the sinc functions is used as a basic pulse so that only the Nyquist bandwidth is required for the channel. In order for these systems to be tolerant to the timing jitter in the receiver, the eye pattern should be open horizontally. It is proved that an eye opening condition which has been understood only as a sufficiency becomes a necessity as well. As its result, having a spectral null at teh Nyquist frequency is shown to have the same meaning as eye opening.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.70-73
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• 1984

By generalizing the concept of nonlinear switching filter, a transmission scheme for the PRS system is constructed. A hardware implementation of the transmission system is presented and its relations with the conventional system are measured. Our system provides the same speed as the traditional PRS system for a bandlimited channel, but has smaller ISI, Timing-jitter and maximum overshoot. Hence this technique improves speed-tolerance and power of the PRS system.