• 전자공학회논문지
• /
• 제51권10호
• /
• pp.87-95
• /
• 2014

본 논문에서는 이중 채널 CIS(CMOS Image Sensor) 인터페이스를 위한 수신기 설계에 대해서 기술한다. 두 채널은 각각 CTLE(Continuous-Time Linear Equalizer)를 포함하며 샘플러, 병렬 변환기 그리고 clocking 회로로 구성되어 있다. Clocking 회로는 PLL, PI, CDR을 포함한다. CDR은 PI 기반이며 OSPD(Over Sampling Phase Detector)와 FSM(Finite State Machine)을 추가하여 빠른 락 소요 시간과 지연 시간, 향상된 jitter tolerance를 갖도록 하였다. CTLE는 3 GHz에서 -6 dB 손실을 갖는 채널의 ISI(Inter Symbol Interference)를 제거하며 CDR은 8000 ppm 이하의 주파수 오프셋에 대해 1 baud period 이내의 빠른 락 소요 시간을 갖는다. 65 nm CMOS 공정을 이용하여 설계하였으며 eye diagram에서 최소 368 mV의 전압 마진과 0.93 UI의 시간 마진을 갖는다.

• 전자공학회논문지
• /
• 제50권12호
• /
• pp.71-79
• /
• 2013

본 논문에서는 이퀄라이저 적응기(adaptation)를 포함하는 12.5 Gb/s 저전력 수신단 설계에 대해서 기술한다. 샘플러와 직렬 변환기를 사용한 저전력 아날로그 이퀄라이저 적응기를 구현함으로써 채널과 칩 공정 변화에 능동적으로 적응할 수 있으며 그 적응 원리에 대해서 설명한다. 또한 저전력을 위한 전압 모드 송신기의 접지 기반 차동 신호를 수신하는 기술에 대해서 설명하였다. 17.6 dB의 피킹 이득을 갖는 CTLE(Continuous Time Linear Equalizer)는 6.25 GHz에서 -21 dB 손실을 갖는 채널의 길게 늘어지는 ISI(Inter Symbol Interference)를 제거한다. 45 nm CMOS 공정을 이용하여 eye diagram에서 200 mV의 전압 마진과 0.75 UI의 시간 마진을 갖고 0.87 mW/Gb/s의 낮은 전력 소모를 유지한다.

• 한국자동차공학회논문집
• /
• 제19권3호
• /
• pp.146-153
• /
• 2011

American NREL (National Renewable Energy Laboratory) reported that BDF20 could reduce PM, CO, SOx, and cancerogenic matters by 13.6%, 9.3%, 17.6%, and 13% respectively, compared to diesel fuel. BDF20 has been being tested on garbage trucks and official vehicles at Seoul City, which is positive on air environment, but negative on combustion by higher viscosity in winter season. This study investigated the combustion characteristics by applying pilot injection for improving the deterioration of combustibility caused by the higher viscosity of the BDF20 with the combustion flames taken by a high-speed camera and the cylinder pressure diagram. A 4-cycle single-cylinder diesel engine was remodeled to a visible 2-cycle engine taking the flame photographs, which has a common-rail injection system. The test was done laboratory temperature at $5{\sim}6^{\circ}C$. The results obtained are summarized as follows, (1) In the case of without pilot injection, the flame propagation speed was slowed and the maximum combustion pressure became lower. The phenomena became further aggravated as the fuel viscosity gets higher. (2) In the case of with pilot injection, early stage of combustion such as rapid ignition timing and flame propagation was activated since intermediate products formed by pilot injection act as a catalyst for combustion of main fuel.

• 대한기계학회논문집
• /
• 제9권5호
• /
• pp.548-554
• /
• 1985

본 논문에서는 디이젤기관의 연소소음의 저감을 최종목표로 하여 Wiebe의 연 소함수에 의해 근사시킨 열발생속도의 변화가 디이젤기관의 연소소음 및 도시열효율에 미치는 영향에 관하여 수치실험을 통하여 해석검토하였다.

• International Journal of Automotive Technology
• /
• 제2권1호
• /
• pp.1-7
• /
• 2001

This paper presents further investigation into the effect of over-expansion cycle in a spark-ignition engine. On the basis of the results obtained in previous studies, several combinations of late-closing (LC) of intake valve and expansion ratio were tested using a single-cylinder production engine. A large volume of intake capacity was inserted into the intake manifold to simulate multi-cylinder engines. With the large capacity volume, LC can decrease the pumping loss and then increase the mechanical efficiency. Increasing the expansion ratio from 11 to 23.9 with LC application can produce about 13% improvement of thermal efficiency which was suggested to be caused by the increased cycle efficiency. The decrease of compression ratio from 11 to 5.5 gives little effect on the thermal efficiency if the expansion ratio could be kept constant. Thus, the expansion ratio is revealed to be a determining factor for cycle efficiency, while compression ratio is no more important, which suggests the usefulness of controlling the intake charge with intake valve closure timing. These were successfully explained by simple thermodynamic calculation and thus the mechanism could be verified by the estimation.

• Journal of Ecology and Environment
• /
• 제31권3호
• /
• pp.207-211
• /
• 2008

We investigated the leaf demography of a temperate woody liana, Akebia trifoliata, in a temperate forest in Japan, Akebia is semi-evergreen: some leaves are shed before winter, while others remain through the winter. Previous studies of semi-evergreen species found that variation in leaf life span was caused by variation in the timing of leaf emergence, Leaves that appeared just before winter over-wintered, while leaves appearing earlier were shed, However, it is unclear whether leaves of the same cohort (i.e., leaves that appear at the same time within a single site) show variation in life span under the effect of strong seasonality. To separate variation in life span among the leaves in each cohort from variation among cohorts, we propose a new method - the single leaf diagram, which shows the emergence and death of each leaf. Using single leaf diagrams, our study revealed that Akebia leaves within a cohort showed substantial variation in life span, with some over-wintering and some not. In addition, leaves on small ramets in the understory showed great variation in life span, while leaves on large ramets, which typically reach higher positions in the forest canopy, have shorter lives, As a result, small ramets were semi-evergreen, whereas large ramets were deciduous, The longer lives of leaves on small ramets can be interpreted as a shade-adaptive strategy in understory plants.

• Progress in Superconductivity
• /
• 제6권1호
• /
• pp.7-12
• /
• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2010년도 춘계학술대회 논문집
• /
• pp.1630-1641
• /
• 2010

LCC can be defined as "the sum of present values of investment costs, capital costs, installation costs, energy costs, operating costs, maintenance costs, and disposal costs over the life-time of the project, product, or measure." LCCA involves estimating the costs and timing associated with each alternative over a selected analysis period and conversion of those costs to economically comparable values considering the time-value of money. The several Excel-Based LCC tools found on the internet are described in this paper. Also, This paper performed an analysis of the existing LCC commercial tools, assessing various aspects of each program. The goal was to evaluate the best features of each tool and to identify the requirements for LCC evaluation of Urban Transit Vehicle. The LCC tools are developed to address problems in many different areas and a tool developed and structured for one area cannot generally be used in another area. No general LCC tool exists and if one is needed for Urban Transit Vehicle it has to be developed by the project. Since a full LCC can be very complex it is likely that this Excel-Based LCC tool should be a small and simple tool for quick cost estimates. This paper presents a LCC tool consisting of eight excel sheets, which are "Project", "CBS", "PBS", "PM", "CM", "Others", "LCC Result" and "Diagram".

• Nuclear Engineering and Technology
• /
• 제47권4호
• /
• pp.443-453
• /
• 2015

A hybrid safety injection tank (H-SIT) can enhance the capability of an advanced power reactor plus (APR+) during a station black out (SBO) that is accompanied by a severe accident. It may a useful alternative to an electric motor. The operations strategy of the H-SIT has to be investigated to achieve maximum utilization of its function. In this study, the master logic diagram (i.e., an analysis for identifying the differences between an H-SIT and a safety injection pump) and an accident case classification were used to determine the parameters of the H-SIT operation. The conditions that require the use of an H-SIT were determined using a decision-making process. The proper timing for using an H-SIT was also analyzed by using the Multi-dimensional Analysis of Reactor Safety (MARS) 1.3 code (Korea Atomic Energy Research Institute, Daejeon, South Korea). The operation strategy analysis indicates that a H-SIT can mitigate five types of failure: (1) failure of the safety injection pump, (2) failure of the passive auxiliary feedwater system, (3) failure of the depressurization system, (4) failure of the shutdown cooling pump (SCP), and (5) failure of the recirculation system. The results of the MARS code demonstrate that the time allowed for recovery can be extended when using an H-SIT, compared with the same situation in which an H-SIT is not used. Based on the results, the use of an H-SIT is recommended, especially after the pilot-operated safety relief valve (POSRV) is opened.

• Progress in Superconductivity
• /
• 제6권2호
• /
• pp.104-107
• /
• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.