• Journal of Korean Society of Forest Science
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• v.23 no.1
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• pp.35-39
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• 1974

After lasting heavy storm, the overfow from the top of soil saving dam may follow if the outlet is not precisely designed and it causes great damages as a result. Therefore, the peak rate of flood must be premeditated at the time of dam construction and many kinds of erosion control measures should also be constructed to protect against the effects of oveflow causing the damages. In this paper, the daily maximum amounts of precipitation from 1904 to 1972 are used as samples of this statistical analysis for the previous purpose and studying local ranges are limited the number of areas to two; Pusan and Mokpo area, because other areas can not give the data of more than 69 years. Normal distribution, as follows, is used for this statistical study. $$P(X)=\int_{x}^{{\infty}}f(x)dx$$ x: daily maximum amount X: maximum of x P(X): probability to exceed X value The estimates, which are the resultants of statistical analysis, can be locally compared with the real values (daily maximum amounts) by diagram, whether the former truly coincides with the latter. As a result, statistical method canot be used for the premeditation of the amount as well as timing of heavy storms because the estimates donot coincide with the real values in this analysis.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• Journal of Astronomy and Space Sciences
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• v.36 no.2
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• pp.75-86
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• 2019

UV Psc is a typical RS CVn type system undergoing dynamic chromosphere activity. We performed photometric observations of the system in 2015 and secured new BVR light curves showing well-defined photometric waves. In this paper, we analyzed the light curves using Wilson-Devinney binary code and investigated the orbital period of the system. The combination of our light curve synthesis with the spectroscopic solution developed by previous investigators yielded the absolute parameters as: $M_1=1.104{\pm}0.042M_{\odot}$, $R_1=1.165{\pm}0.025R_{\odot}$, and $L_1=1.361{\pm} 0.041L_{\odot}$ for the primary star, and $M_2=0.809{\pm}0.082M_{\odot}$, $R_2=0.858{\pm}0.018R_{\odot}$, and $L_2=0.339 {\pm}0.010L_{\odot}$ for the secondary star. The eclipse timing diagram for accurate CCD and photoelectric timings showed that the orbital period may vary either in a downward parabolic manner or a quasi-sinusoidal pattern. If the latter is adopted as a probable pattern for the period change, a more plausible account for the cyclic variation may be the light time effect caused by a circumbinary object rather than an Applegate-mechanism occurring via variable surface magnetic field strengths.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.13 no.1
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• pp.1-14
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• 2014

The expansion of the physical road in response to changes in social conditions and policy of the country has reached the limit. In order to alleviate congestion on the existing road to reconsider the effectiveness of this method should be asking. Currently, how to collect traffic information for management of the intersection is limited to point detection systems. Intelligent Transport Systems (ITS) was the traffic information collection system of point detection method such as through video and loop detector in the past. However, intelligent transportation systems of the next generation(C-ITS) has evolved rapidly in real time interval detection system of collecting various systems between the pedestrian, road, and car. Therefore, this study is designed to evaluate the development of an algorithm for queue length based real-time traffic signal control methodology. Four coordinates estimate on time-space diagram using the travel time each individual vehicle collected via the interval detector. Using the coordinate value estimated during the cycle for estimating the velocity of the shock wave the queue is created. Using the queue length is estimated, and determine the signal timing the total queue length is minimized at intersection. Therefore, in this study, it was confirmed that the calculation of the signal timing of the intersection queue is minimized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.12
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• pp.1216-1227
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• 2013

GNSS(Global Navigation Satellite System) is now being widely used in both civilian and military applications where accurate positioning and timing information are required and it is considered as a representative convergence technique in IT-Military application techniques. However, GNSS has low sensitivity level of GNSS receivers and is vulnerable to jamming signal, since the signals come from the satellite located at approximately 20,000 Km above the earth. The studies for the anti-jamming techniques in military applications have been passively performed in the domestic, because the information related GNSS are dependent on the countries that have GNSS. In this paper, we show the effect of jammer ERP by analyzing the link budget of GPS J/S power as a function of distance between jammer and receiver. Also, we categorize the anti-jamming techniques based on the functional block diagram of GNSS receiver structure and analyze the recent anti-jamming GNSS products and their technologies developed in domestic and foreign countries.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.651-659
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• 2004

The Fast Handover protocol ［1］ provides seameless handover in wireless If networks by minimizing handover latency, which uses anticipation based on layer 2 (L2) trigger information. Therefore, it incurs higher signaling costs compared with the basic Mobile U protocol. Furthermore, since the L2 trigger is based on fluctuating wireless channel states, the handover anticipation may sometimes be incorrect. In the case of incorrect anticipation, unnecessary buffer space may be used for the purpose of providing a smooth handover. Therefore, it is essentical to analyze these overhead costs, in order to evaluate and compare the performance of Fast Handover with that of the basic Mobile U protocol. In this paper, we analyzed the overhead associated with Fast Handover including the signaling cost and the packet delivery cost. We formulated these costs based on a timing diagram and compared Fast Handover with basic Mobile Ipv6 in terms of their packet loss rates and buffer requirements. Also, we studied the impact of the L2 triggering time on the total overhead cost.

• The korean journal of orthodontics
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• v.4 no.1
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• pp.31-40
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• 1974

The age of maximum growth increments-the adolescent spurt-is not only of developmental interest but is used as a marker for timing other growth events. And the mandibular growth rate follows the general growth curve, it is essential for an orthodontist to take the current and exact information about physical growth of patients. The author measured and studied the body height and weight of 11,694 children living in Seoul, and calculated out the mean, standard deviation, coefficient value, annual increments, percentage increments of each value, and made diagram to compare it with others. 1. The growth curve shows linear increment tendency until 17 years of age in male, 15 years in female. 2. The annual increment curves of body height and weight reveals the most peak value in 14-16 years in male and 11-14 years in female. 3. During 11-14 years of age, female growth exceed the male growth in the body height growth. And in weight growth, female growth exceed the male growth during 6-7 years and 11-12 years to show twice crossing. 4. It seemed that until 11-12 years in male and until 9-10 years in female the height growth show the priority to weight growth. And from 17 years in male and 15 years in female the body growth reveals the balanced growth pattern. 5. The time of changes of standard deviation curves of body height and weight coincided with that of annual increments. 6. The prominent high value of body height and weight in the comparison with other data may be due to the secioeconomical and nutritional, environmental influence. 7. The growth accerlation phenomena was detectable.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of IKEEE
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• v.18 no.2
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• pp.263-271
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• 2014

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.72-81
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• 2006

In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.