• Broadcasting and Media Magazine
• /
• v.7 no.3
• /
• pp.75-82
• /
• 2002

In this report, the complexity analysis of the JVT(Joint Video Team) codec, which has jointly developed the next video coding standard, is performed. Three types of configurations in terms of coding efficiency are set and the analysis of the memory band width and computation time for each configuration is performed. ATOMIUM complexity analysis tool is used for both the memory access statistics and computation time calculation of JVT codec. Also the complexity of each video coding tool in the encoder and decoder is shown in relative complexity.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.13 no.11
• /
• pp.5773-5784
• /
• 2019

ARIA is an involutory SPN block cipher. Its block size is 128-bit and the master key sizes are 128/192/256-bit, respectively. Accordingly, they are called ARIA-128/192/256. As we all know, ARIA is a Korean Standard block cipher nowadays. This paper focuses on the security of ARIA against impossible differential attack. We firstly construct a new 4-round impossible differential of ARIA. Furthermore, based on this impossible differential, a new 7-round impossible differential attack on ARIA-256 is proposed in our paper. This attack needs 2¹¹⁸ chosen plaintexts and 2²¹⁰ 7-round encryptions. Comparing with the previous best result, we improve both the data complexity and time complexity. To our knowledge, it is the best impossible differential attack on ARIA-256 so far.

• ETRI Journal
• /
• v.34 no.1
• /
• pp.110-113
• /
• 2012

We propose a very-low-complexity lattice-reduction (LR) algorithm for multi-input multi-output detection in time-varying channels. The proposed scheme reduces the complexity by performing LR in a block-wise manner. The proposed scheme takes advantage of the temporal correlation of the channel matrices in a block and its impact on the lattice transformation matrices during the LR process. From this, the proposed scheme can skip a number of redundant LR processes for consecutive channel matrices and performs a single LR in a block. As the Doppler frequency decreases, the complexity reduction efficiency becomes more significant.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.4
• /
• pp.227-233
• /
• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Journal of Computing Science and Engineering
• /
• v.10 no.2
• /
• pp.68-73
• /
• 2016

An efficient texture compression method is proposed based on a block matching process between the current block and the previously encoded blocks. Texture mapping is widely used to improve the quality of rendering results in real-time applications. For fast texture mapping, it is important to find an optimal trade-off between compression efficiency and computational complexity. Low-complexity methods (e.g., ETC1 and DXT1) have often been adopted in real-time rendering applications because conventional compression methods (e.g., JPEG) achieve a high compression ratio at the cost of high complexity. We propose a block matching-based compression method that can achieve a higher compression ratio than ETC1 and DXT1 while maintaining computational complexity lower than that of JPEG. Through a comparison between the proposed method and existing compression methods, we confirm our expectations on the performance of the proposed method.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.12
• /
• pp.42-49
• /
• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• KIPS Transactions on Computer and Communication Systems
• /
• v.8 no.2
• /
• pp.29-34
• /
• 2019

Priority queues, one of the fundamental data structures, have been studied for a long time by computer scientists. This paper proposes an implicit double-ended priority queue, called IMI-heap, in which insert operation takes constant amortized time and each of removal operation of the minimum key or the maximum key takes O(logn) time. To the author's knowledge, all implicit double-ended priority queues that have been published, perform insert, removeMin and removeMax operations in O(logn) time each. So, the proposed IMI-heap is superior than the published heaps in terms of insertion time complexity.The abstract should concisely state what was done, how it was done, principal results, and their significance.

• Journal of Korea Multimedia Society
• /
• v.9 no.8
• /
• pp.1020-1029
• /
• 2006

Realization of high-capacity quality-of-service router needs fair packet schedulers with a lower complexity. Timestamp based fair packet schedulers have the ideal complexity of O(log V), where V is the maximum number of admitted flows, but it has been recently reduced to O(1) using bin concept. However, the latency property was deteriorated and the bandwidth utilization was also declined. In addition, traffic flows requiring strong delay bound may not be admitted. To overcome these problems, this paper proposes a Mini-Bin based Start-Time (MBST) scheduler with variable complexity and evaluates its performance. The MBST scheduler uses the timestamp calculation scheme of start-time based schedulers to enhance the bandwidth utilization and also introduces mini-bin concept to improve the latency, The performance evaluation shows that the proposed scheduler can reduce the complexity of the legacy start-tine based schedulers by $1.8{\sim}5$ times without deteriorating the bandwidth utilization property.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.4
• /
• pp.1-8
• /
• 2008

In orthogonal frequency division multiplexing (OFDM) system the time selectivity of wireless channel introduces intercarrier interference (ICI), which degrades system performance in proportion to Doppler frequency. To mitigate the ICI effect, we can generally employ a classical zero-forcing (ZF) equalizer. However, the ZF scheme requires an inverse of a large matrix, which results in prohibitively high computational complexity. In this paper, we propose a low complexity ZF equalization scheme for suppressing the ICI caused by highly time-varying channels in OFDM systems. From the fact that the ICI on a subcarrier is mainly caused by several neighboring subcarriers, the proposed scheme exploits a numerical approximation for matrix inversion based on Neumann's Series (truncated second order). To further improve performance, the partial ICI cancellation technique is also used with reduced complexity. Complexity analysis and simulation results show that the proposed scheme provides the advantage of reducing computational complexity significantly, while achieving almost the same performance as that of the classical ZF a roach.

• Journal of information and communication convergence engineering
• /
• v.5 no.1
• /
• pp.54-58
• /
• 2007

A real-time frame-layer rate control algorithm with a token bucket traffic shaper is proposed for distortion variation minimization. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. The proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performances than the existing rate control method.